Abstract:
A memory setting method and apparatus the method including obtaining, by a processor that is in a non-uniform memory access architecture (NUMA) system and that has at least two memories, performance of the at least two memories upon the processor starting, and setting, based on the performance of the at least two memories, at least one of the at least two memories as a local memory, and setting, based on the performance, at least one of the at least two memories as a remote memory, where performance of the local memory is better than performance of the remote memory.
Abstract:
Embodiments of the present invention disclose a method for switching an NC link, a processor system, and a node, where the processor system includes more than two nodes capable of communicating with each other, each node includes a node controller NC chip, a host bus adapter HBA apparatus, and at least one CPU, the NC chip is connected to each CPU in a node where the NC chip is located, and the HBA apparatus is connected to each CPU in a node where the HBA apparatus is located; an NC link borne by the NC chip is corresponding to an HBA link borne by the HBA apparatus. By using an HBA apparatus to deploy a redundant link, the cost of deploying the redundant link is reduced effectively under a premise of ensuring the reliability of the processor system.
Abstract:
Embodiments of the present invention disclose a method for switching an NC link, a processor system, and a node, where the processor system includes more than two nodes capable of communicating with each other, each node includes a node controller NC chip, a host bus adapter HBA apparatus, and at least one CPU, the NC chip is connected to each CPU in a node where the NC chip is located, and the HBA apparatus is connected to each CPU in a node where the HBA apparatus is located; an NC link borne by the NC chip is corresponding to an HBA link borne by the HBA apparatus. By using an HBA apparatus to deploy a redundant link, the cost of deploying the redundant link is reduced effectively under a premise of ensuring the reliability of the processor system.