公开(公告)号：US20190229739A1

公开(公告)日：2019-07-25

申请号：US16255663

申请日：2019-01-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ding LI ,  Shuai Du ,  Hongpei Wang

IPC: H03M1/06 ,  H03M1/40 ,  H03M1/74

Abstract: Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

公开(公告)号：US20210043720A1

公开(公告)日：2021-02-11

申请号：US17077329

申请日：2020-10-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ding LI ,  Shuai DU ,  Yixing CHU

IPC: H01L49/02 ,  H01C7/00 ,  H01C1/14

Abstract: A polysilicon resistor is disclosed, to reduce a voltage coefficient of the polysilicon resistor. The polysilicon resistor includes: a polysilicon layer (101), a voltage module (102), and a substrate layer (103), where the voltage module (102) is configured to transmit a voltage on the polysilicon layer (101) to the substrate layer (103).

公开(公告)号：US20180191363A1

公开(公告)日：2018-07-05

申请号：US15857651

申请日：2017-12-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ding LI ,  Shuai DU ,  Hongpei WANG

IPC: H03M1/06 ,  H03M1/40

CPC classification number: H03M1/068 ,  H03M1/00 ,  H03M1/1009 ,  H03M1/406 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

Abstract: Embodiments of the present invention provide a digital-to-analog conversion circuit, where the digital-to-analog conversion circuit includes a signal amplitude detector and a digital-to-analog converter. When the signal amplitude detector detects a low signal amplitude, a first current module in the digital-to-analog converter operates normally and a second current module in the digital-to-analog converter stops operating. In addition, when stopping operating, the second current module is in a state of a third bias voltage and a fourth bias voltage that are generated by a second bias circuit. When the amplitude detector detects a high signal amplitude subsequently, the second current module resumes normal operation. After operating normally, the second current module switches back to a first bias voltage and a second bias voltage that are generated by a first bias circuit. This reduces a nonlinearity problem caused before a second current module resumes normal operation.

公开(公告)号：US20140247072A1

公开(公告)日：2014-09-04

申请号：US14194291

申请日：2014-02-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jinxiu LIU ,  Shubao GUO ,  Ding LI

IPC: H03K21/02

CPC classification number: H03K21/02 ,  G04G3/04 ,  G06F1/14 ,  G06F1/32 ,  H03L1/00

Abstract: The present invention provides a correction circuit. The correction circuit includes a frequency dividing circuit, a frequency dividing coefficient operation circuit, a built-in temperature collection circuit, and a power-on and power-off detection circuit. The built-in temperature collection circuit is configured to collect a temperature of the chip; the power-on and power-off detection circuit is configured to detect power-on and power-off of the chip; the frequency dividing coefficient operation circuit is configured to calculate, according to the temperature of the chip collected by the built-in temperature collection circuit when the power-on and power-off detection circuit detects that the chip is powered off, a frequency dividing coefficient, and output the frequency dividing coefficient to the frequency dividing circuit; and the frequency dividing circuit is configured to provide, according to the frequency dividing coefficient output by the frequency dividing coefficient operation circuit, a timing pulse for a real-time clock.

Abstract translation: 本发明提供一种校正电路。 校正电路包括分频电路，分频系数运算电路，内置温度采集电路以及通电断电检测电路。 内置的温度采集电路被配置为收集芯片的温度; 上电断电检测电路被配置为检测芯片的上电和断电; 分频系数运算电路被配置为当上电和断电检测电路检测到芯片断电时根据由内置温度采集电路收集的芯片的温度来计算分频系数 并将分频系数输出到分频电路; 并且分频电路被配置为根据由分频系数运算电路输出的分频系数提供实时时钟的定时脉冲。