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公开(公告)号：US20250095565A1
公开(公告)日：2025-03-20
申请号：US18552217
申请日：2022-07-29
Inventor： Xuehuan FENG , Pan XU , Yongqian LI
IPC: G09G3/3225
Abstract: A driving signal generation circuit includes a first node generation circuit, a second node generation circuit, a third node generation circuit, a first control node control circuit, a second control node control circuit and an output circuit; the second control node control circuit is configured to control to connect the second control node and the first clock signal terminal under the control of the potential of the second control node, and control the potential of the second control node according to the potential of the second node; the output circuit is configured to output corresponding driving signal through the driving signal output terminal under the control of the potential of the first control node and the potential of the second control node.
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公开(公告)号：US20220122533A1
公开(公告)日：2022-04-21
申请号：US17271914
申请日：2020-05-13
Inventor： Can YUAN , Pan XU , Yongqian LI , Zhidong YUAN
IPC: G09G3/3233
Abstract: Pixel driving method for driving pixel unit display driving method and display substrate are provided. The pixel unit includes pixel driving circuit, including driving transistor, storage capacitor, and data writing circuit, the driving transistor has control electrode coupled to first terminals of the data writing circuit and the storage capacitor, and first electrode coupled to second terminal of the storage capacitor, and second terminal of the data writing circuit is coupled to data line. The pixel driving method includes: loading a data voltage into the data line, and controlling the first and second terminals of the data writing circuit to be connected; controlling the data line to be floating, and maintaining connection between the first and second terminals of the data writing circuit to reduce gate-source voltage of the driving transistor; and controlling the first and second terminals of the data writing circuit to be disconnected.
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公开(公告)号：US20210335269A1
公开(公告)日：2021-10-28
申请号：US17206121
申请日：2021-03-19
Inventor： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.
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公开(公告)号：US20210074196A1
公开(公告)日：2021-03-11
申请号：US17015475
申请日：2020-09-09
Inventor： Xuehuan FENG , Pan XU
Abstract: The present disclosure relates to the field of display technology and, in particular, to a gate driving structure, an array substrate, and a display device. The gate driving structure may include: a base substrate; a shift register formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.
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公开(公告)号：US20240268148A1
公开(公告)日：2024-08-08
申请号：US17914686
申请日：2021-11-18
Inventor： Zhidong YUAN , Pan XU , Jun LIU , Can YUAN , Yongqian LI
IPC: H10K59/121 , H10K59/12 , H10K59/131
CPC classification number: H10K59/1213 , H10K59/1201 , H10K59/1216 , H10K59/131
Abstract: A display panel includes a plurality of sub-pixels, a sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes at least a driving transistor and a storage capacitor. The display panel further includes a substrate, and a first gate conductive layer, a semiconductor layer and a second gate conductive layer that are disposed on the substrate. The first gate conductive layer includes a first electrode plate of the storage capacitor. The semiconductor layer includes an active layer pattern of the driving transistor. At least part of the active layer pattern of the driving transistor and at least part of the first electrode plate are disposed in a same layer. The second gate conductive layer includes a second electrode plate of the storage capacitor and a gate electrode of a driving transistor electrically connected to the second electrode plate.
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Patent Agency Ranking
公开(公告)号：US20220398982A1
公开(公告)日：2022-12-15
申请号：US17635471
申请日：2020-12-26
Inventor： Zhidong YUAN , Pan XU , Can YUAN , Yongqian LI , Zhongyuan WU
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: An array substrate includes: a substrate, at least one gate driving circuit and at least one clock signal line that are located on a same side of the substrate. The gate driving circuit includes a plurality of cascaded shift registers located in different rows, the plurality of shift registers are divided into at least two groups of shift registers, each group of shift registers includes at least one shift register, located in a same column. A gate driving circuit in the at least one gate driving circuit corresponds to at least one clock signal line. The clock signal line includes a main body transmission section configured to transmit a clock signal, and at least two branch transmission sections connected to the main body transmission section. Each branch transmission section is connected to a clock signal input terminal of each shift register in a respective group of shift registers.
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公开(公告)号：US20220189406A1
公开(公告)日：2022-06-16
申请号：US17352319
申请日：2021-06-20
Inventor： Xuehuan FENG , Yongqian LI , Pan XU
IPC: G09G3/3266 , G09G3/3225 , G11C19/28
Abstract: The present disclosure provides a shift register unit, a gate driving circuitry and a method for driving the gate driving circuitry. The shift register unit includes an input circuitry, a first latch circuitry, a second latch circuitry and an output end. The input circuitry is configured to output an input control signal to the first latch circuitry in accordance with a first level signal, a second level signal and a first ON signal. The first latch circuitry is configured to output an output signal as a gate driving signal via the output end in accordance with a first clock signal and the input control signal, and latch the output signal. The second latch circuitry is configured to output a second ON signal in accordance with a second clock signal and the output signal, and latch the second ON signal.
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公开(公告)号：US20240365595A1
公开(公告)日：2024-10-31
申请号：US18247230
申请日：2022-04-29
Inventor： Zhidong YUAN , Pan XU , Huifeng WANG , Can YUAN , Zhongyuan WU
IPC: H10K59/122 , H10K59/12 , H10K59/88
CPC classification number: H10K59/122 , H10K59/1201 , H10K59/88
Abstract: Embodiments of the present disclosure provide a display panel, a display device, and a method for preparing a display panel. The display panel has a display area and a peripheral area, the display panel including a pixel defining layer including a plurality of first pixel defining blocks in the display area parallelly arranged in a first direction, and adjacent first pixel defining blocks having different columns of pixel defining openings, and at least one second pixel defining block in the peripheral area as an extension of at least one first pixel defining block in a second direction to the peripheral area, each second pixel defining block including a plurality of columns of pixel defining openings, a column number which is greater than or equal to the difference in the column numbers of pixel defining openings of two adjacent first pixel defining blocks.
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公开(公告)号：US20240215422A1
公开(公告)日：2024-06-27
申请号：US17791262
申请日：2021-09-28
Inventor： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN
IPC: H10K59/88 , G01R31/28 , G09G3/3233 , G09G3/3266 , H10K71/70
CPC classification number: H10K59/88 , G01R31/2884 , G09G3/3233 , G09G3/3266 , H10K71/70 , G09G2300/0408 , G09G2300/0842 , G09G2310/0286 , G09G2310/08 , G09G2330/12
Abstract: A display panel, and a test method thereof, a display apparatus, each subpixel of the pixel array of the display panel includes a pixel circuit, a first signal line configured to provide a scanning signal to the pixel circuit, a scan driver circuit configured to provide the scanning signal to the pixel circuit and includes a shift register and a clock signal line in the display area; a test circuit board in the non-display area and including a test pad; and a test lead in the non-display area and electrically connected with the test pad. The first signal line includes a first part in the display area and a second part in the non-display area, the first part extends substantially along the first direction.
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10.发明申请公开(公告)号：US20230125979A1
公开(公告)日：2023-04-27
申请号：US18077269
申请日：2022-12-08
Inventor： Xuehuan FENG , Pan XU
Abstract: The present disclosure relates to the field of display technology, and in particular, to a gate driving structure, an array substrate and a display device. The gate driving structure may include: a base substrate; a shift register, formed on the base substrate, and including a plurality of thin film transistors and at least one capacitor, the capacitor being coupled to the thin film transistor; and a signal wiring group, formed on the base substrate, and including a plurality of signal wirings spaced apart from each other, the signal wiring being coupled to the thin film transistor. An orthographic projection of the capacitor on the base substrate is at least partially overlapped with an orthographic projection of the signal wiring group on the base substrate.
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