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1.发明授权Non-volatile memory device with uncorrectable information region and operation method using the same 有权具有不可校正信息区域的非易失性存储器件和使用其的操作方法公开(公告)号：US08612836B2
公开(公告)日：2013-12-17
申请号：US13025463
申请日：2011-02-11
Applicant: Han Bin Yoon , Mi Kyoung Jang , Jin-Hyuk Lee
Inventor： Han Bin Yoon , Mi Kyoung Jang , Jin-Hyuk Lee
IPC: H03M13/00
CPC classification number: G06F12/0246 , G06F11/1068 , G06F2212/1032 , G06F2212/7207 , H03M13/05
Abstract: The non-volatile memory system includes a non-volatile memory and a controller. The non-volatile memory includes a data region including a sector region for storing sector data, and an uncorrectable information region for storing uncorrectable sector information on the sector region. The controller includes an information generation unit for generating the uncorrectable sector information that indicates whether the sector region is assigned to an uncorrectable sector region, according to a command output from a host.
Abstract translation: 非易失性存储器系统包括非易失性存储器和控制器。 非易失性存储器包括包括用于存储扇区数据的扇区区域的数据区域和用于在扇区区域上存储不可校正扇区信息的不可校正信息区域。 控制器包括信息生成单元，用于根据从主机输出的命令，生成指示扇区是否分配给不可校正扇区的不可校正扇区信息。
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公开(公告)号：US09443580B2
公开(公告)日：2016-09-13
申请号：US14408512
申请日：2012-06-28
Applicant: Naveen Muralimanohar , Han Bin Yoon , Norman Paul Jouppi
Inventor： Naveen Muralimanohar , Han Bin Yoon , Norman Paul Jouppi
CPC classification number: G11C11/5678 , G11C7/1057 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/06 , G11C16/26 , G11C2211/5642
Abstract: A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from the memory cell, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.
Abstract translation: 多级单元存储器包括存储两个或更多位信息的存储单元; 耦合到所述存储单元的感测电路; 以及包括具有第一页缓冲器和第二页缓冲器的分页页缓冲器的行缓冲器结构。 感测电路操作以从存储器单元读取，将第一位置于第一页缓冲器和第二页缓冲器之一中，并将第二位置于第一页缓冲器和第二页缓冲器之一中。
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3.发明申请公开(公告)号：US20120047318A1
公开(公告)日：2012-02-23
申请号：US13166216
申请日：2011-06-22
Applicant: Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Kwang Ho Kim , Hyuck-Sun Kwon
Inventor： Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Kwang Ho Kim , Hyuck-Sun Kwon
IPC: G06F12/02
CPC classification number: G06F3/0616 , G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F13/1668 , G06F2206/1014
Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device; and a controller configured to receive a write command from a host and program write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.
Abstract translation: 提供半导体存储装置及其节流方法。 半导体存储装置包括非易失性存储装置; 以及控制器，被配置为从主机接收写入命令，并且响应于写入命令将程序写入从主机接收到非易失性存储器设备的数据。 控制器在接收到来自主机的写入数据和/或在将写入数据编程到非易失性存储器件之后插入空闲时间。
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4.发明授权Method and apparatus to interface semiconductor storage device and host to provide performance throttling of semiconductor storage device 有权接口半导体存储设备和主机以提供半导体存储设备的性能调节的方法和设备公开(公告)号：US09037778B2
公开(公告)日：2015-05-19
申请号：US13212404
申请日：2011-08-18
Applicant: Han Bin Yoon , Dong Gi Lee , Hyuck-Sun Kwon
Inventor： Han Bin Yoon , Dong Gi Lee , Hyuck-Sun Kwon
CPC classification number: G06F3/0616 , G06F3/0638 , G06F3/0659 , G06F3/0679
Abstract: A method and apparatus to interface a semiconductor storage device and a host in order to provide performance throttling of the semiconductor storage device. In the method, the semiconductor storage can receive a setting request command from the host. The semiconductor storage device sets a performance throttling parameter to a particular value in response to the setting request command. The semiconductor storage device can send to the host a setting response signal indicating completion of the setting of the performance throttling parameter.
Abstract translation: 一种用于将半导体存储设备和主机接口以便提供半导体存储设备的性能调节的方法和设备。 在该方法中，半导体存储器可以从主机接收设置请求命令。 半导体存储装置响应于设置请求命令将性能调节参数设置为特定值。 半导体存储装置可以向主机发送指示性能调节参数的设置的完成的设置响应信号。
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Patent Agency Ranking
5.发明授权公开(公告)号：US08856424B2
公开(公告)日：2014-10-07
申请号：US13166216
申请日：2011-06-22
Applicant: Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Kwang Ho Kim , Hyuck-Sun Kwon
Inventor： Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Kwang Ho Kim , Hyuck-Sun Kwon
CPC classification number: G06F3/0616 , G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F13/1668 , G06F2206/1014
Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device, and a controller configured to receive a write command from a host and program and to write data received from the host to the non-volatile memory device in response to the write command. The controller inserts idle time after receiving the write data from the host and/or after programming the write data to the non-volatile memory device.
Abstract translation: 提供半导体存储装置及其节流方法。 半导体存储装置包括非易失性存储装置，以及控制器，被配置为从主机和程序接收写入命令，并且响应写入命令将从主机接收到的数据写入到非易失性存储器装置。 控制器在接收到来自主机的写入数据和/或在将写入数据编程到非易失性存储器件之后插入空闲时间。
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公开(公告)号：US20150162078A1
公开(公告)日：2015-06-11
申请号：US14408512
申请日：2012-06-28
Applicant: Naveen Muralimanohar , Han Bin Yoon , Norman Paul Jouppi
Inventor： Naveen Muralimanohar , Han Bin Yoon , Norman Paul Jouppi
CPC classification number: G11C11/5678 , G11C7/1057 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/06 , G11C16/26 , G11C2211/5642
Abstract: A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from and write to the memory device, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.
Abstract translation: 多级单元存储器包括存储两个或更多位信息的存储单元; 耦合到所述存储单元的感测电路; 以及包括具有第一页缓冲器和第二页缓冲器的分页页缓冲器的行缓冲器结构。 感测电路操作以读取和写入存储器件，将第一位置于第一页缓冲器和第二页缓冲器之一中，并将第二位置于第一页缓冲器和第二页缓冲器之一中。
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7.发明授权公开(公告)号：US08862807B2
公开(公告)日：2014-10-14
申请号：US13166257
申请日：2011-06-22
Applicant: Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
Inventor： Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
IPC: G06F12/00
CPC classification number: G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F2206/1014
Abstract: A semiconductor storage device (SSD) and a method of throttling performance of the SSD are provided. The method can include includes gathering at least two workload data items related with to a workload of the semiconductor storage device, estimating the workload using the at least two workload data items, and throttling the performance of the semiconductor storage device according to the estimated workload. Accordingly, a workload that the semiconductor storage device will undergo can be estimated.
Abstract translation: 提供了一种半导体存储设备（SSD）和一种节制SSD性能的方法。 该方法可以包括收集与半导体存储设备的工作负载相关的至少两个工作负载数据项，使用至少两个工作负载数据项估计工作量，以及根据估计的工作量来调节半导体存储设备的性能。 因此，可以估计半导体存储装置将经历的工作量。
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8.发明授权公开(公告)号：US08862806B2
公开(公告)日：2014-10-14
申请号：US13166131
申请日：2011-06-22
Applicant: Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
Inventor： Han Bin Yoon , Yeong-Jae Woo , Dong Gi Lee , Young Kug Moon , Hyuck-Sun Kwon
CPC classification number: G06F3/0613 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F2206/1014
Abstract: A semiconductor storage device and a method of throttling performance of the same are provided. The semiconductor storage device includes a non-volatile memory device configured to store data in a non-volatile state, and a controller configured to control the non-volatile memory device. The controller calculates a new performance level, compares the calculated performance level with a predetermined reference, and determines the calculated performance level as an updated performance level according to the comparison result.
Abstract translation: 提供半导体存储装置及其节流方法。 半导体存储装置包括被配置为以非易失性状态存储数据的非易失性存储装置，以及被配置为控制非易失性存储装置的控制器。 控制器计算新的性能水平，将计算的性能水平与预定参考值进行比较，并根据比较结果将计算出的性能水平确定为更新的性能水平。
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9.发明授权Method and apparatus for controlling page buffer of non-volatile memory device 有权用于控制非易失性存储器件的页缓冲器的方法和装置公开(公告)号：US08614913B2
公开(公告)日：2013-12-24
申请号：US13028313
申请日：2011-02-16
Applicant: Han Bin Yoon , Yeong-Jae Woo , Jung Been Im
Inventor： Han Bin Yoon , Yeong-Jae Woo , Jung Been Im
IPC: G11C11/34
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/3418
Abstract: A method of managing a page buffer of a non-volatile memory device comprises programming least significant bit (LSB) page data from an LSB page buffer into a page of memory cells, and retaining the LSB page data in the LSB page buffer until most significant bit (MSB) page data corresponding to the LSB page data is programmed in the page.
Abstract translation: 管理非易失性存储器件的页面缓冲器的方法包括将LSB页面缓冲器中的最低有效位（LSB）页数据编程到存储器单元的页中，并将LSB页数据保留在LSB页缓冲器中，直到最高 在页面中编程对应于LSB页数据的位（MSB）页数据。
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