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公开(公告)号：US20100225398A1
公开(公告)日：2010-09-09
申请号：US12399485
申请日：2009-03-06
Applicant: Hajime SHIBATA
Inventor： Hajime SHIBATA
CPC classification number: H03F3/4521 , H03F3/211 , H03F2203/21112 , H03F2203/21157 , H03F2203/45008 , H03F2203/45342 , H03F2203/45354 , H03F2203/45481
Abstract: An embodiment of a multi-path, multi-oxide-thickness amplifier circuit includes a first amplifier having at least one thin-oxide output transistor, and a second amplifier having at least one thick-oxide output transistor. The first and second amplifiers are connected in parallel with each other between an input terminal and an output terminal of the amplifier circuit. The thin-oxide output transistor has a gate-oxide layer thickness that is less than a gate-oxide layer thickness of the thick-oxide output transistor.
Abstract translation: 多路径多氧化物厚度放大器电路的实施例包括具有至少一个薄氧化物输出晶体管的第一放大器和具有至少一个厚氧化物输出晶体管的第二放大器。 第一和第二放大器在放大器电路的输入端和输出端之间彼此并联连接。 薄氧化物输出晶体管具有小于厚氧化物输出晶体管的栅极 - 氧化物层厚度的栅极 - 氧化物层厚度。
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公开(公告)号：US20150042501A1
公开(公告)日：2015-02-12
申请号：US14524729
申请日：2014-10-27
Applicant: Hajime SHIBATA
Inventor： Hajime SHIBATA
Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。
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公开(公告)号：US20130113569A1
公开(公告)日：2013-05-09
申请号：US13292835
申请日：2011-11-09
Applicant: Hajime SHIBATA , Richard SCHREIER , Wenhua YANG
Inventor： Hajime SHIBATA , Richard SCHREIER , Wenhua YANG
CPC classification number: H03F3/45183 , H03F3/45434 , H03F3/45439 , H03F2203/45318 , H03F2203/45332 , H03F2203/45352 , H03F2203/45481 , H03F2203/45512 , H03F2203/45516 , H03F2203/45534 , H03F2203/45536 , H03F2203/45544 , H03F2203/45594 , H03F2203/45631 , H03F2203/45648 , H03F2203/45701
Abstract: An operational amplifier can include a plurality of amplifiers connected to form a plurality of amplification paths extending from an input terminal to an output terminal of the operational amplifier. An amplifier in one of the amplification paths can include an intrinsic amplification-transistor capacitance connected between a first amplifier input and a first amplifier output, and a cross-coupling capacitor connected between the first amplifier input and a second amplifier output. A plurality of the amplification paths can include series-connected amplifiers connected in parallel with the cross-coupled amplifier. The cross-coupling capacitor can have a capacitance value selected as a function of the intrinsic capacitance and a gain experienced between the amplifier inputs and outputs. The operational amplifier can include an AC coupling capacitor connected in series with the cross-coupled amplifier. The operational amplifier can be arranged in feedback configuration.
Abstract translation: 运算放大器可以包括多个放大器，其连接以形成从运算放大器的输入端子到输出端子延伸的多个放大路径。 一个放大路径中的放大器可以包括连接在第一放大器输入端和第一放大器输出端之间的本征放大晶体管电容以及连接在第一放大器输入端和第二放大器输出端之间的交叉耦合电容器。 多个放大路径可以包括与交叉耦合放大器并联连接的串联放大器。 交叉耦合电容器可以具有根据本征电容选择的电容值和放大器输入和输出之间经历的增益。 运算放大器可以包括与交叉耦合放大器串联连接的AC耦合电容器。 运算放大器可以布置在反馈配置中。
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Patent Agency Ranking
公开(公告)号：US20110163813A1
公开(公告)日：2011-07-07
申请号：US13047694
申请日：2011-03-14
Applicant: Hajime SHIBATA
Inventor： Hajime SHIBATA
CPC classification number: H03F3/4521 , H03F3/211 , H03F2203/21112 , H03F2203/21157 , H03F2203/45008 , H03F2203/45342 , H03F2203/45354 , H03F2203/45481
Abstract: An amplifier circuit can include a first supply terminal to receive a first reference voltage; a second supply terminal to receive a second reference voltage; a first pair of circuit paths extending between the first and second supply terminals and including a respective output terminal, the first pair of circuit paths including a first pair of transistors, each having a gate connected to a respective one of the input terminals and a source connected to the first supply terminal, and a second pair of transistors, each having a gate connected via a first impedance to a gate of a respective first transistor, and a source coupled to the second supply terminal. The amplifier circuit can also include a second pair of circuit paths extending between the first and second supply terminals, the second pair of circuit paths including a third pair of transistors, each having a gate connected to one of the input terminals, and a source connected to the first supply terminal, and a fourth pair of transistors, each having a source connected to the second supply terminal, and a gate connected via a second impedance to a gate of a second transistor from a respective first circuit path.
Abstract translation: 放大器电路可以包括用于接收第一参考电压的第一电源端子; 第二供电端子，用于接收第二参考电压; 第一对电路路径，其在所述第一和第二电源端子之间延伸并且包括相应的输出端子，所述第一对电路路径包括第一对晶体管，每个晶体管具有连接到所述输入端子中的相应一个的栅极和源极 连接到第一电源端子，以及第二对晶体管，每个晶体管具有经由第一阻抗连接到相应第一晶体管的栅极的栅极，以及耦合到第二电源端子的源极。 放大器电路还可以包括在第一和第二电源端子之间延伸的第二对电路路径，第二对电路路径包括第三对晶体管，每个晶体管具有连接到输入端之一的栅极，源极连接 以及第四对晶体管，每个晶体管具有连接到第二电源端子的源极，以及通过第二阻抗从相应的第一电路路径连接到第二晶体管的栅极的栅极。
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公开(公告)号：US20130033291A1
公开(公告)日：2013-02-07
申请号：US13204505
申请日：2011-08-05
Applicant: Hajime SHIBATA , Wenhua YANG , David Nelson ALLDRED
Inventor： Hajime SHIBATA , Wenhua YANG , David Nelson ALLDRED
IPC: H03K3/00 , H03K17/687
CPC classification number: H03K3/356104
Abstract: A switch circuit can include an impedance selection switch and a multi-output-resistance switch driver. The impedance selection switch can electrically connect an impedance to an input of an amplifier in response to a driver output signal, and include at least one transistor. The multi-output-impedance switch driver may provide the driver output signal to the switch, and have a first, relatively higher output resistance when providing a first logic state of the driver output signal to turn on the switch, and a second, relatively lower output resistance when providing a second logic state of the driver output signal to turn off the switch. The ratio of the first output resistance to the second output resistance can be greater than a selected predetermined ratio value.
Abstract translation: 开关电路可以包括阻抗选择开关和多输出电阻开关驱动器。 阻抗选择开关可以响应于驱动器输出信号将阻抗电连接到放大器的输入，并且包括至少一个晶体管。 多输出阻抗开关驱动器可以向开关提供驱动器输出信号，并且当提供驱动器输出信号的第一逻辑状态以导通开关时具有第一相对较高的输出电阻，以及第二相对较低的 当提供驱动器输出信号的第二逻辑状态以关闭开关时的输出电阻。 第一输出电阻与第二输出电阻的比可以大于所选择的预定比值。
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公开(公告)号：US20100283545A1
公开(公告)日：2010-11-11
申请号：US12463231
申请日：2009-05-08
Applicant: Hajime SHIBATA
Inventor： Hajime SHIBATA
CPC classification number: H03F3/211 , H03F3/45179 , H03F3/45183 , H03F3/45188 , H03F3/4521 , H03F3/45475 , H03F2203/21142 , H03F2203/45091 , H03F2203/45138 , H03F2203/45481
Abstract: An embodiment of an amplifier circuit includes a plurality of amplifiers connected between input and output terminals to form at least partially parallel amplification paths between the terminals. A first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common first series-connected amplifier, and a second plurality of the amplification paths have different first amplifiers. Optionally, a third plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a fourth plurality of the amplification paths have different last amplifiers. Alternatively, a first plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common last series-connected amplifier, and a second plurality of the amplification paths have different last amplifiers. In the alternative embodiment, optionally a third plurality of the amplification paths include series-connected pluralities of the amplifiers and share a common first series-connected amplifier, and a fourth plurality of the amplification paths have different first amplifiers.
Abstract translation: 放大器电路的实施例包括连接在输入和输出端子之间的多个放大器，以在端子之间形成至少部分并行的放大路径。 第一多个放大路径包括串联连接的多个放大器并且共享共同的第一串联连接放大器，并且第二多个放大路径具有不同的第一放大器。 可选地，第三多个放大路径包括串联连接的多个放大器并且共享共同的最后串联放大器，并且第四多个放大路径具有不同的最后的放大器。 或者，第一多个放大路径包括串联连接的多个放大器并且共享共同的最后串联放大器，并且第二多个放大路径具有不同的最后的放大器。 在替代实施例中，可选地，第三多个放大路径包括串联连接的多个放大器并且共享公共的第一串联连接的放大器，并且第四多个放大路径具有不同的第一放大器。
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公开(公告)号：US20140266821A1
公开(公告)日：2014-09-18
申请号：US13869454
申请日：2013-04-24
Applicant: Hajime SHIBATA
Inventor： Hajime SHIBATA
IPC: H03M1/00
Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.
Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。
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公开(公告)号：US20130043957A1
公开(公告)日：2013-02-21
申请号：US13212762
申请日：2011-08-18
Applicant: Hajime SHIBATA
Inventor： Hajime SHIBATA
CPC classification number: H03H11/245 , H03B5/00 , H03B2201/011 , H03B2201/018 , H03B2201/0208 , H03B2201/025
Abstract: A tunable impedance circuit can include a fixed impedance and one or more impedance selection circuits. Each impedance selection circuit can include a first impedance connected to a first interface terminal, a second impedance connected to a second interface terminal, and a plurality of series-connected transistors connected between the first and second impedances. Each impedance selection circuit can also include a plurality of drive impedance networks connected to gates, sources, drains, bodies, and isolation regions of the series-connected transistors, and a control circuit to provide a plurality of control signals to the drive impedance networks to turn on and turn off the series-connected transistors. For each impedance selection circuit, turning on and turning off the respective plurality of series-connected transistors can bring the series combination of the respective first and second impedances into and out of electrical communication with, e.g., into and out of parallel with, the fixed impedance.
Abstract translation: 可调谐阻抗电路可以包括固定阻抗和一个或多个阻抗选择电路。 每个阻抗选择电路可以包括连接到第一接口端子的第一阻抗，连接到第二接口端子的第二阻抗以及连接在第一和第二阻抗之间的多个串联连接的晶体管。 每个阻抗选择电路还可以包括连接到串联连接晶体管的栅极，源极，漏极，主体和隔离区域的多个驱动阻抗网络，以及控制电路，以向驱动阻抗网络提供多个控制信号 打开并关闭串联晶体管。 对于每个阻抗选择电路，导通和关断相应的多个串联晶体管可以使相应的第一和第二阻抗的串联组合进入和流出与例如固定的 阻抗。
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