公开(公告)号：US20100062598A1

公开(公告)日：2010-03-11

申请号：US12618523

申请日：2009-11-13

申请人： Hae-Jung LEE ,  Sang-Hoon Cho ,  Suk-Ki Kim

发明人： Hae-Jung LEE ,  Sang-Hoon Cho ,  Suk-Ki Kim

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76849

摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

公开(公告)号：US08030205B2

公开(公告)日：2011-10-04

申请号：US12618523

申请日：2009-11-13

申请人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

发明人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76849

摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

公开(公告)号：US07648909B2

公开(公告)日：2010-01-19

申请号：US11321533

申请日：2005-12-30

申请人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

发明人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76849

摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

公开(公告)号：US20060246708A1

公开(公告)日：2006-11-02

申请号：US11321533

申请日：2005-12-30

申请人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

发明人： Hae-Jung Lee ,  Sang-Hoon Cho ,  Suk-Ki Kim

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/32115 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76849

摘要： A method for fabricating a semiconductor device includes forming an inter-layer insulation layer on a substrate; forming openings in the inter-layer insulation layer; forming a metal barrier layer in the openings and on the inter-layer insulation layer; forming a first conductive layer on the metal barrier layer and filled in the openings; etching the first conductive layer to form interconnection layers in the openings and to expose portions of the metal barrier layer, the interconnection layers being inside the openings and at a depth from a top of the openings; etching the exposed portions of the metal barrier layer to obtain a sloped profile of the metal barrier layer at top lateral portions of the openings; forming a second conductive layer over the inter-layer insulation layer, the interconnection layers and the metal barrier layer with the sloped profile; and patterning the second conductive layer to form metal lines.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成层间绝缘层; 在层间绝缘层中形成开口; 在开口和层间绝缘层上形成金属阻挡层; 在所述金属阻挡层上形成第一导电层并填充在所述开口中; 蚀刻所述第一导电层以在所述开口中形成互连层并且暴露所述金属阻挡层的部分，所述互连层位于所述开口内部以及在距所述开口顶部的深度处; 蚀刻金属阻挡层的暴露部分以在开口的顶侧部分处获得金属阻挡层的倾斜轮廓; 在所述层间绝缘层上形成第二导电层，所述互连层和所述金属阻挡层具有所述倾斜轮廓; 并且图案化第二导电层以形成金属线。

公开(公告)号：US07858476B2

公开(公告)日：2010-12-28

申请号：US11928056

申请日：2007-10-30

申请人： Yong-Tae Cho ,  Suk-Ki Kim ,  Sang-Hoon Cho

发明人： Yong-Tae Cho ,  Suk-Ki Kim ,  Sang-Hoon Cho

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3086

摘要： A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a first recess in the substrate and a passivation layer on sidewalls of the first recess using the hard mask pattern as an etch barrier, and forming a second recess by etching a bottom portion of the first recess using the passivation layer as an etch barrier, wherein a width of the second recess is greater than that of the first recess.

摘要翻译： 一种用于制造半导体器件的方法包括：在衬底上形成硬掩模图案，在衬底中形成第一凹槽，并使用硬掩模图案作为蚀刻阻挡层，在第一凹槽的侧壁上形成钝化层，并形成第二凹槽 使用钝化层蚀刻第一凹部的底部作为蚀刻阻挡层，其中第二凹部的宽度大于第一凹部的宽度。

公开(公告)号：US08040294B2

公开(公告)日：2011-10-18

申请号：US11984416

申请日：2007-11-16

申请人： Suk-Ki Kim

发明人： Suk-Ki Kim

IPC分类号： G09G3/28

CPC分类号： G09G3/2965 ,  G09G2330/045

摘要： A plasma display apparatus includes: an electrode of a discharge cell; a first transistor having a first terminal and a second terminal, the second terminal being connected to the electrode; a first capacitor having a first terminal to receive a control signal having either a low level voltage or a high level voltage; a push-pull circuit including a first power terminal, a second power terminal connected to the first terminal of the first transistor, an input terminal connected to a second terminal of the first capacitor, and an output terminal connected to a gate of the first transistor, the push-pull circuit outputting either a voltage of the first power terminal or a voltage of the second power terminal to the output terminal; a floating power source having a positive terminal connected to the first power terminal and a negative terminal connected to the second power terminal; and a first diode connected between the first terminal of the first transistor and the second terminal of the first capacitor.

摘要翻译： 一种等离子体显示装置，包括：放电单元的电极; 第一晶体管，具有第一端子和第二端子，所述第二端子连接到所述电极; 第一电容器，具有用于接收具有低电平电压或高电平电压的控制信号的第一端子; 推挽电路，包括第一电源端子，连接到第一晶体管的第一端子的第二电源端子，连接到第一电容器的第二端子的输入端子以及连接到第一晶体管的栅极的输出端子 所述推挽电路将所述第一电源端子的电压或所述第二电力端子的电压输出到所述输出端子; 具有连接到所述第一电源端子的正极端子和连接到所述第二电力端子的负极端子的浮动电源; 以及连接在第一晶体管的第一端子和第一电容器的第二端子之间的第一二极管。

公开(公告)号：US07952278B2

公开(公告)日：2011-05-31

申请号：US12318461

申请日：2008-12-30

申请人： Min-Suk Lee ,  Jong-Seo Choi ,  Matulevich Yuri ,  Suk-Ki Kim ,  Young-Su Kim ,  Deok-Hyun Kim ,  Hee-Young Chu ,  Soon-Sung Suh

发明人： Min-Suk Lee ,  Jong-Seo Choi ,  Matulevich Yuri ,  Suk-Ki Kim ,  Young-Su Kim ,  Deok-Hyun Kim ,  Hee-Young Chu ,  Soon-Sung Suh

IPC分类号： H01J17/49

CPC分类号： H01J11/40 ,  H01J11/12 ,  Y10T428/24479

摘要： A protective layer of a plasma display panel includes smoky magnesium oxide, the smoky magnesium oxide having single crystal magnesium oxide with a plurality of cavities therein.

摘要翻译： 等离子体显示面板的保护层包括烟雾氧化镁，该烟雾氧化镁具有单晶氧化镁，其中具有多个空腔。

公开(公告)号：US20080062076A1

公开(公告)日：2008-03-13

申请号：US11819848

申请日：2007-06-29

申请人： Jeong-Hoon Kim ,  Jung-Pil Park ,  Suk-Ki Kim ,  Young-Jun Jeon

发明人： Jeong-Hoon Kim ,  Jung-Pil Park ,  Suk-Ki Kim ,  Young-Jun Jeon

IPC分类号： G09G3/28

CPC分类号： G09G3/296 ,  G09G3/292 ,  G09G3/293 ,  G09G2310/0289 ,  G09G2330/028

摘要： In a plasma display, a first electrode and a second electrode of a transistor may be respectively coupled to a scan electrode and a power source for supplying a scan voltage. The plasma display may include a scan electrode, a first transistor, a first resistor, and a second resistor. The first transistor may include a first electrode electrically coupled to the scan electrode, a second electrode electrically coupled to the power source and a control electrode. The first resistor may be electrically coupled between the scan electrode and the control electrode of the first transistor. The second resistor may be electrically coupled between the control electrode of the transistor and the power source.

摘要翻译： 在等离子体显示器中，晶体管的第一电极和第二电极可以分别耦合到扫描电极和用于提供扫描电压的电源。 等离子体显示器可以包括扫描电极，第一晶体管，第一电阻器和第二电阻器。 第一晶体管可以包括电耦合到扫描电极的第一电极，电耦合到电源的第二电极和控制电极。 第一电阻器可以电耦合在第一晶体管的扫描电极和控制电极之间。 第二电阻器可以电耦合在晶体管的控制电极和电源之间。

公开(公告)号：US20060154801A1

公开(公告)日：2006-07-13

申请号：US11328107

申请日：2006-01-10

申请人： Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Jae-Hyuk Kim ,  Soon-Sung Suh

发明人： Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Jae-Hyuk Kim ,  Soon-Sung Suh

IPC分类号： C04B35/04 ,  H01J17/00 ,  H01J9/24

CPC分类号： H01J11/40 ,  C04B35/04 ,  C04B35/653 ,  C04B2235/3272 ,  C04B2235/3275 ,  C04B2235/3279 ,  C04B2235/3281 ,  C04B2235/443 ,  C04B2235/445 ,  C23C30/00 ,  H01J11/12

摘要： A protecting layer is formed of a magnesium oxide and at least one additional component selected from the group consisting of a copper component selected from copper and a copper oxide, a nickel component selected from nickel and a nickel oxide, a cobalt component selected from cobalt and a cobalt oxide, and an iron component selected from iron and an iron oxide; a composite for forming the protecting layer; a method of forming the protecting layer; and a plasma display panel including the protecting layer. The protecting layer, which is used in a PDP, protects an electrode and a dielectric layer from a plasma ion generated by a gaseous mixture of Ne and Xe, or He, Ne, and Xe, and discharge delay time and dependency of the discharge delay time on temperature can be decreased and sputtering resistance can be increased.

摘要翻译： 保护层由氧化镁和至少一种选自铜和氧化铜的铜成分，选自镍和氧化镍的镍成分，选自钴的钴成分和选自钴的钴成分组成的组中， 钴氧化物和选自铁和氧化铁的铁组分; 用于形成保护层的复合材料; 形成保护层的方法; 以及包括保护层的等离子体显示面板。 用于PDP中的保护层保护电极和电介质层免受由Ne和Xe或He，Ne和Xe的气体混合物产生的等离子体离子，并且放电延迟时间和放电延迟的依赖性 可以降低温度时间，并且可以提高溅射电阻。

公开(公告)号：US08570247B2

公开(公告)日：2013-10-29

申请号：US12503744

申请日：2009-07-15

申请人： Suk-Ki Kim ,  Ji-Hyun Yoo ,  Seong-Joong Kim

发明人： Suk-Ki Kim ,  Ji-Hyun Yoo ,  Seong-Joong Kim

IPC分类号： G09G3/28

CPC分类号： G09G3/2965 ,  G09G3/292

摘要： A plasma display device and method of driving the device is disclosed. The device includes a driving circuit for driving reset, address, and sustain periods during a subfield of a frame. The driving circuit includes a single switch which is used to drive a display electrode both during the reset period and during the sustain period. The switch being used for both periods removes the need for a second switch, thereby reducing manufacturing and design costs.

摘要翻译： 公开了一种驱动该装置的等离子体显示装置和方法。 该装置包括用于在帧的子场期间驱动复位，寻址和维持周期的驱动电路。 驱动电路包括单个开关，其用于在复位期间和维持期期间驱动显示电极。 用于两个时期的开关不需要第二个开关，从而降低制造和设计成本。