Signal processing method and network device

    公开(公告)号:US11991534B2

    公开(公告)日:2024-05-21

    申请号:US17752308

    申请日:2022-05-24

    Inventor: Jie Feng Yiwei Hong

    CPC classification number: H04W16/28 H04B7/0456 H04B7/0617 H04W72/0453

    Abstract: This application provides example signal processing methods, media, and apparatuses. One example method includes obtaining a scattering parameter matrix of passive echoes in an antenna system by a network device. The m virtual user directions are determined by the network device based on the scattering parameter matrix of the passive echoes, where the m virtual user directions are m directions in which total signal strength of the passive echoes is highest, and m is a positive integer. A target beam is formed based on n real user directions and the m virtual user directions, where one or more nulls of the target beam are aligned with the m virtual user directions, n is a positive integer, and n+m≤k.

    DIGITAL PREDISTORTION PROCESSING APPARATUS
    2.
    发明申请

    公开(公告)号:US20190140605A1

    公开(公告)日:2019-05-09

    申请号:US16241674

    申请日:2019-01-07

    Abstract: Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.

    Digital predistortion processing apparatus

    公开(公告)号:US10749485B2

    公开(公告)日:2020-08-18

    申请号:US16241674

    申请日:2019-01-07

    Abstract: Embodiments of the present disclosure provide a digital predistortion processing apparatus, where the apparatus includes an analog-to-digital conversion unit and n digital predistortion elements. The analog-to-digital conversion unit is connected to the n digital predistortion elements. Each digital predistortion element is configured to receive n input signals, perform digital predistortion processing on the n input signals, and then output n processed signals. The analog-to-digital conversion unit is configured to receive the n processed signals, perform signal extraction based on the n processed signals, and output an extracted signal, where a rate of the extracted signal is the same as a rate of each of the n processed signals. For an ultra-large-bandwidth signal, DPD correction may be performed without increasing a technical level of existing components such as an FPGA and an ADC, thereby greatly reducing implementation costs.

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