公开(公告)号：US20170214405A1

公开(公告)日：2017-07-27

申请号：US15410972

申请日：2017-01-20

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shengli Yang ,  Xing Huang

IPC: H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0016 ,  G06F1/06 ,  G06F1/10 ,  G06F5/16 ,  G06F2217/62 ,  H03K19/0175 ,  H03K19/1737 ,  H03K21/026 ,  H03K2217/0054

Abstract: A clock circuit includes a buffer module, N multiplexers, and N clock gating cells. The buffer module includes an input end and N output ends, and is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal from the N output ends, and the N output ends are connected to data ends of the N clock gating cells one to one. Output ends of the N first multiplexers are connected to enabling ends of the N clock gating cells one to one. Each clock gating cell outputs a clock signal from an output end according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end of a corresponding multiplexer and the clock signal received by a data end from an output end of the buffer module.

公开(公告)号：US20240357524A1

公开(公告)日：2024-10-24

申请号：US18758548

申请日：2024-06-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Changfeng Qiu ,  Xing Huang ,  Yangbo Gong

IPC: H04W56/00

CPC classification number: H04W56/001

Abstract: Embodiments of this application disclose a system frame number synchronization method, applied to a communication system defined in the enhanced common public radio interface eCPRI protocol. The communication system includes radio equipment control and radio equipment. The method includes: The radio equipment control generates system frame information, where the system frame information indicates a system frame number; and the radio equipment control sends the system frame information to the radio equipment by using a control plane message. A system frame number used by the radio equipment is consistent with the system frame number used by the radio equipment control.

公开(公告)号：US10904064B2

公开(公告)日：2021-01-26

申请号：US16295248

申请日：2019-03-07

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xinyu Wang ,  Ding Ding ,  Boyun Xie ,  Hongjie Li ,  Xing Huang

IPC: H04L27/26 ,  H04W72/04 ,  H04W28/00 ,  H04L5/00 ,  H04L5/14 ,  H04W72/08 ,  H04W24/10

Abstract: Communication method and base stations are provided. One example includes determining, by a base station, that co-channel interference exists. For N consecutive symbols before a guard period (GP) in a special subframe in a radio frame, the base station sends a signal by using M1 middle resource blocks (RBs) of the N symbols, and reserves use of an RB other than the M1 RBs in the N symbols, where both N and M1 are positive integers.

公开(公告)号：US09800243B2

公开(公告)日：2017-10-24

申请号：US15410972

申请日：2017-01-20

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shengli Yang ,  Xing Huang

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/173 ,  G06F1/06 ,  G06F1/10 ,  G06F5/16

CPC classification number: H03K19/0016 ,  G06F1/06 ,  G06F1/10 ,  G06F5/16 ,  G06F2217/62 ,  H03K19/0175 ,  H03K19/1737 ,  H03K21/026 ,  H03K2217/0054

Abstract: A clock circuit includes a buffer module, N multiplexers, and N clock gating cells. The buffer module includes an input end and N output ends, and is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal from the N output ends, and the N output ends are connected to data ends of the N clock gating cells one to one. Output ends of the N first multiplexers are connected to enabling ends of the N clock gating cells one to one. Each clock gating cell outputs a clock signal from an output end according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end of a corresponding multiplexer and the clock signal received by a data end from an output end of the buffer module.