公开(公告)号：US20170214405A1

公开(公告)日：2017-07-27

申请号：US15410972

申请日：2017-01-20

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shengli Yang ,  Xing Huang

IPC: H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0016 ,  G06F1/06 ,  G06F1/10 ,  G06F5/16 ,  G06F2217/62 ,  H03K19/0175 ,  H03K19/1737 ,  H03K21/026 ,  H03K2217/0054

Abstract: A clock circuit includes a buffer module, N multiplexers, and N clock gating cells. The buffer module includes an input end and N output ends, and is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal from the N output ends, and the N output ends are connected to data ends of the N clock gating cells one to one. Output ends of the N first multiplexers are connected to enabling ends of the N clock gating cells one to one. Each clock gating cell outputs a clock signal from an output end according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end of a corresponding multiplexer and the clock signal received by a data end from an output end of the buffer module.

公开(公告)号：US09800243B2

公开(公告)日：2017-10-24

申请号：US15410972

申请日：2017-01-20

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shengli Yang ,  Xing Huang

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/173 ,  G06F1/06 ,  G06F1/10 ,  G06F5/16

CPC classification number: H03K19/0016 ,  G06F1/06 ,  G06F1/10 ,  G06F5/16 ,  G06F2217/62 ,  H03K19/0175 ,  H03K19/1737 ,  H03K21/026 ,  H03K2217/0054

Abstract: A clock circuit includes a buffer module, N multiplexers, and N clock gating cells. The buffer module includes an input end and N output ends, and is configured to enhance a driving capability of a clock signal received by the input end, and output the clock signal from the N output ends, and the N output ends are connected to data ends of the N clock gating cells one to one. Output ends of the N first multiplexers are connected to enabling ends of the N clock gating cells one to one. Each clock gating cell outputs a clock signal from an output end according to a frequency division logic signal or a gating logic signal received by an enabling end from an output end of a corresponding multiplexer and the clock signal received by a data end from an output end of the buffer module.