公开(公告)号：US20250037749A1

公开(公告)日：2025-01-30

申请号：US18919810

申请日：2024-10-18

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shihui YIN ,  Weiliang JING ,  Bingwu JI ,  Sitong BU ,  Zhengbo WANG ,  Heng LIAO

IPC: G11C11/22

Abstract: This disclosure relates to a bit line reading circuit, a memory, and an electronic device. An example bit line reading circuit includes a bit line connected to a ferroelectric memory cell. The bit line reading circuit further includes a reference line, a sense amplifier, and a precharge circuit. The sense amplifier and the precharge circuit are separately connected to the bit line and the reference line. The bit line reading circuit further includes a first switch connected to the bit line between the sense amplifier and the precharge circuit, and a second switch connected to the reference line between the sense amplifier and the precharge circuit.

公开(公告)号：US20230276636A1

公开(公告)日：2023-08-31

申请号：US18311598

申请日：2023-05-03

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jeffrey Junhao XU ,  Weiliang JING ,  Sitong BU ,  Yichen FANG ,  Ying WU ,  Zhaozhao HOU ,  Wanliang TAN ,  Heng ZHANG ,  Yu ZHANG

IPC: H10B53/30 ,  H10B53/20

CPC classification number: H10B53/30 ,  H10B53/20

Abstract: Example ferroelectric memories and storage devices are described One example ferroelectric memory includes at least one bit cell. A bit cell in the at least one bit cell includes a plurality of ferroelectric capacitors and a first transistor. The first transistor includes a first gate, a first channel, a first source, and a first drain. The first source and the first drain are located at two ends of the first channel. One electrode of each of the plurality of ferroelectric capacitors is formed on the first gate.