Integrated Circuit Package Apparatus Deployed with Antenna and Method for Manufacturing Integrated Circuit Package Apparatus

    公开(公告)号:US20190081013A1

    公开(公告)日:2019-03-14

    申请号:US16185869

    申请日:2018-11-09

    Abstract: An integrated circuit package apparatus deployed with an antenna and a method for manufacturing an integrated circuit package apparatus, where the integrated circuit package apparatus includes a package substrate, an antenna, a chip, and a connection circuit. The package substrate includes at least one ground plane, the antenna is deployed on an external surface of one side of the package substrate and is located on one side of the at least one ground plane, the chip and the connection circuit are deployed on the other side of the at least one ground plane, where the antenna is isolated from the chip and the connection circuit using the at least one ground plane, and the antenna is coupled to the chip using the connection circuit and a first metal through hole in a thickness direction of the package substrate.

    Integrated circuit package apparatus deployed with antenna and method for manufacturing integrated circuit package apparatus

    公开(公告)号:US11049823B2

    公开(公告)日:2021-06-29

    申请号:US16185869

    申请日:2018-11-09

    Abstract: An integrated circuit package apparatus deployed with an antenna and a method for manufacturing an integrated circuit package apparatus, where the integrated circuit package apparatus includes a package substrate, an antenna, a chip, and a connection circuit. The package substrate includes at least one ground plane, the antenna is deployed on an external surface of one side of the package substrate and is located on one side of the at least one ground plane, the chip and the connection circuit are deployed on the other side of the at least one ground plane, where the antenna is isolated from the chip and the connection circuit using the at least one ground plane, and the antenna is coupled to the chip using the connection circuit and a first metal through hole in a thickness direction of the package substrate.

    Chip package device
    4.
    发明授权

    公开(公告)号:US11430760B2

    公开(公告)日:2022-08-30

    申请号:US16931819

    申请日:2020-07-17

    Abstract: A chip package device includes a chip, and a first substrate and a second substrate that are disposed opposite to each other, where the chip is disposed on a surface that is of the first substrate and that faces the second substrate. The chip is electrically connected to the first substrate through a first conductive part, the first substrate is electrically connected to the second substrate through a second conductive part, and a heat dissipation passage is formed between the chip and the second substrate through a thermally conductive layer. The chip package device may further include a molding compound that is configured to wrap the chip. The thermally conductive layer disposed between the chip and the second substrate can quickly dissipate a large amount of heat generated by the chip to the second substrate so that the chip maintains a normal temperature.

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