公开(公告)号：US20170287875A1

公开(公告)日：2017-10-05

申请号：US15619532

申请日：2017-06-11

Applicant: HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO. LTD.

Inventor： Ziyang GAO ,  Xunqing SHI ,  Shi Wo CHOW

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L22/12 ,  H01L22/20 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/17 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094

Abstract: A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.