公开(公告)号：US09966345B1

公开(公告)日：2018-05-08

申请号：US15463627

申请日：2017-03-20

Applicant: Google Inc.

Inventor： Gregory Sizikov ,  Woon Seong Kwon

IPC: H01L23/495 ,  H01L23/62 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/62 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1427 ,  H01L2924/1433

Abstract: An IC package is configured to receive a voltage regulator and a load. The IC package includes a plurality of buildup layers disposed on a plurality of core layers. The buildup layers have a top side that includes first and second surface features for receiving the voltage regulator and the load, respectively. First and second pluralities of vias connect the first and second surface features, respectively, to a buildup conductor layer and a core conductor layer. The buildup conductor layer includes a substantially solid or continuous conductor plane extending across and connected to the first and second pluralities of vias. The buildup conductor layer defines a gap between the first and second pluralities of vias, the gap partially separating a portion of the conductor plane connected to the first plurality of vias from a portion connected to the second plurality of vias.

公开(公告)号：US10025047B1

公开(公告)日：2018-07-17

申请号：US15488237

申请日：2017-04-14

Applicant: Google Inc.

Inventor： Hong Liu ,  Ryohei Urata ,  Woon Seong Kwon ,  Teckgyu Kang

IPC: G02B6/42 ,  H05K3/30 ,  H01L23/00 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32

Abstract: Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.