公开(公告)号：US09275861B2

公开(公告)日：2016-03-01

申请号：US13927685

申请日：2013-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Li Yang ,  Kejia Wang ,  Ashish Baraskar ,  Bin Yang ,  Shurong Liang

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/20

CPC classification number: H01L21/02658 ,  H01L21/02373 ,  H01L21/0243 ,  H01L21/02538 ,  H01L29/045 ,  H01L29/20

Abstract: One method disclosed herein includes forming a patterned mask layer above a surface of a semiconductor substrate, performing at least one etching process through the patterned mask layer to define a plurality of intersecting ridges that define a ridged surface in the substrate, and forming a Group III-V material on the ridged surface of the substrate. An illustrative device disclosed herein includes a Group IV substrate having a ridged surface comprised of a plurality of intersecting ridges and a Group III-V material layer positioned on the ridged surface of the Group IV substrate.

Abstract translation: 本文公开的一种方法包括在半导体衬底的表面上形成图案化掩模层，通过图案化掩模层执行至少一个蚀刻工艺，以限定在衬底中限定脊状表面的多个相交脊，并形成第III组 -V在基板的脊状表面上的材料。 本文公开的说明性装置包括具有由多个相交脊组成的脊状表面的第IV族衬底和位于第IV族衬底的脊状表面上的III-V族材料层。

公开(公告)号：US20150286764A1

公开(公告)日：2015-10-08

申请号：US14245868

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Li Yang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing e overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.

Abstract translation: 本文公开的至少一种方法涉及为使用自对准双图案（SADP）工艺制造的集成电路的整体图案布局，在金属层的第一轨道上形成具有第一宽度的第一金属特征 使用SADP工艺，在金属层的第二轨道上形成具有第二宽度的第二金属特征。 第二条轨道与第一条轨道相邻。 该方法还包括在第一金属特征和第二金属特征之间形成电连接，以提供具有第三宽度的有效单个金属图案，该第三宽度是第一宽度和第二宽度之和，使得第一和第二特征可以使用SADP分解 处理; 并且将第一和第二金属特征的e整体图案布局分解成心轴掩模图案和块掩模图案。

公开(公告)号：US09582629B2

公开(公告)日：2017-02-28

申请号：US14245868

申请日：2014-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Li Yang ,  Jongwook Kye

IPC: H01L21/76 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing the overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.

Abstract translation: 本文公开的至少一种方法涉及为使用自对准双图案（SADP）工艺制造的集成电路的整体图案布局，在金属层的第一轨道上形成具有第一宽度的第一金属特征 使用SADP工艺，在金属层的第二轨道上形成具有第二宽度的第二金属特征。 第二条轨道与第一条轨道相邻。 该方法还包括在第一金属特征和第二金属特征之间形成电连接，以提供具有第三宽度的有效单个金属图案，该第三宽度是第一宽度和第二宽度之和，使得第一和第二特征可以使用SADP分解 处理; 并且将具有第一和第二金属特征的整体图案布局分解成心轴掩模图案和块掩模图案。

公开(公告)号：US09400863B2

公开(公告)日：2016-07-26

申请号：US14687477

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Soo Han Choi ,  Li Yang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

公开(公告)号：US08969199B1

公开(公告)日：2015-03-03

申请号：US14054251

申请日：2013-10-15

Applicant: Globalfoundries Inc.

Inventor： Lei Yuan ,  Jason Eugene Stephens ,  Li Yang ,  Soo Han Choi

IPC: H01L21/312 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0334 ,  H01L21/31144 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11859

Abstract: One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括使用三种图案化的光致抗蚀剂蚀刻掩模图案化硬掩模层，其中对应于交叉耦合栅极接触结构的一部分但不是全部的第一特征存在于第一 三个图案化的光致抗蚀剂蚀刻掩模和对应于交叉耦合栅极接触结构的一部分但不是全部的第二特征存在于三个图案化的光致抗蚀剂蚀刻掩模的第二或第三个中，使用 图案化的硬掩模层作为蚀刻掩模，并且在绝缘材料层中的沟槽中形成交叉耦合栅极接触结构。

公开(公告)号：US09158879B2

公开(公告)日：2015-10-13

申请号：US14017594

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Soo Han Choi ,  Li Yang ,  Jongwook Kye

IPC: G06F17/30 ,  G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

Abstract translation: 公开了在IC设计中能够产生颜色不可确定的多边形的方法和装置。 实施例包括：确定在IC设计中水平延伸的多个第一路线，所述多条第一路线中的​​每条路线被放置在所述IC设计的多个相等间隔的垂直位置之一上; 确定第二路线是否与所述多个等间隔垂直位置的垂直位置之一重叠; 以及基于所述第二路由是否重叠的确定来选择所述第二路由的设计规则。