公开(公告)号：US09972634B2

公开(公告)日：2018-05-15

申请号：US15234066

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Krottenthaler ,  Martin Mazur

IPC: H01L27/115 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L27/11546 ,  H01L27/1207 ,  H01L29/161 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.

公开(公告)号：US20180047738A1

公开(公告)日：2018-02-15

申请号：US15234066

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Krottenthaler ,  Martin Mazur

IPC: H01L27/115 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/161 ,  H01L27/12 ,  H01L29/788

CPC classification number: H01L27/11546 ,  H01L27/1207 ,  H01L29/161 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.