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    UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME
    1.
    发明申请
    UNIQUE BI-LAYER ETCH STOP TO PROTECT CONDUCTIVE STRUCTURES DURING A METAL HARD MASK REMOVAL PROCESS AND METHODS OF USING SAME 审中-公开
    金属硬掩模去除过程中独特的双层蚀刻保护导电结构及其使用方法

    公开(公告)号：US20160372413A1

    公开(公告)日：2016-12-22

    申请号：US14741636

    申请日：2015-06-17

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Anbu Selvam Mahalingam ,  Ashwini Chandrashekar ,  Craig Child

    IPC分类号： H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/768

    CPC分类号： H01L23/53295 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53238

    摘要： One method includes, among other things, forming a bi-layer etch stop layer above a conductive contact comprised of titanium nitride, the bi-layer etch stop layer consisting of an upper second layer that is made of aluminum nitride, forming a patterned etch mask comprised of a layer of titanium nitride above a second layer of insulating material, with the bi-layer etch stop layer in position above the conductive contact, performing an etching process through the patterned etch mask to define a cavity in the second layer of insulating material, performing a second etching process to remove at least the layer of titanium nitride of the patterned etch mask, forming an opening in the bi-layer etch stop layer so as to thereby expose a portion of the conductive contact and forming a conductive structure in the cavity that is conductively coupled to the exposed portion of the conductive contact.

    摘要翻译： 一种方法包括在包括氮化钛的导电接触层之上形成双层蚀刻停止层，双层蚀刻停止层由由氮化铝制成的上部第二层组成，形成图案化的蚀刻掩模 包括在第二绝缘材料层上方的氮化钛层，双层蚀刻停止层位于导电接触点上方的位置，通过图案化的蚀刻掩模执行蚀刻工艺，以在第二绝缘材料层中限定空腔 ，执行第二蚀刻工艺以去除图案化蚀刻掩模的至少所述氮化钛层，在双层蚀刻停止层中形成开口，从而暴露导电接触的一部分并在其中形成导电结构 导电地耦合到导电触点的暴露部分的腔。

    Devices and methods of reducing damage during BEOL M1 integration
    4.
    发明授权
    Devices and methods of reducing damage during BEOL M1 integration 有权

    公开(公告)号：US10340177B2

    公开(公告)日：2019-07-02

    申请号：US15048493

    申请日：2016-02-19

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ashwini Chandrashekar ,  Anbu Selvam Km Mahalingam ,  Craig Michael Child, Jr.

    IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/00 ,  H01L23/522 ,  H01L23/532

    摘要： Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.