公开(公告)号：US20240039853A1

公开(公告)日：2024-02-01

申请号：US18327504

申请日：2023-06-01

Applicant: Fujitsu Limited

Inventor： Norikazu HIKIMOCHI ,  Kazuto NISHIMURA ,  Shoji MIYAKE ,  Jiro TAKEZAWA ,  Yoshikazu SABETTO

IPC: H04L47/22 ,  H04L45/24 ,  H04L47/2425

CPC classification number: H04L47/225 ,  H04L45/245 ,  H04L47/2433

Abstract: A communication device to be coupled to a transmission device with MC-LAG, the communication device includes a first output port coupled to an other communication device within a first route, a second output port within a second route, an iTAS device arranged in each of the first output port and the second output port, and configured to preferentially output a high priority flow, based on a set an iTAS period, a memory, and a processor coupled to the memory and configured to acquire a first iTAS period set to the iTAS device arranged in the first output port and a second iTAS period set to an iTAS device arranged in a third output port in the other communication device within the first route, and set an iTAS period of the iTAS device arranged in the second output port, based on the first and second iTAS periods.

公开(公告)号：US20140177443A1

公开(公告)日：2014-06-26

申请号：US14069900

申请日：2013-11-01

Applicant: FUJITSU LIMITED

Inventor： Kazuto NISHIMURA

IPC: H04L12/819

CPC classification number: H04L47/12 ,  H04L47/56

Abstract: A relay apparatus that transfers data with an identifier corresponding to a transfer rate attached thereto and stores data as a transfer target to adjust the transfer rate, the relay apparatus includes multiple buffers that are respectively associated with multiple time regions that serve as targets to be successively read from a current point of time onward, each buffer having a capacity to store an amount of data determined in accordance with the transfer rate of the identifier, and a controller that reduces a size of a buffer corresponding to a second time region to be smaller than a size of a buffer corresponding to a first time region prior to the second time region in accordance with a time difference between the current point of time and the second time region.

Abstract translation: 一种中继装置，其以与附加的传送速率对应的标识符进行数据的传送，存储作为传送对象的数据来调整传送速度，所述中继装置具有分别与作为连续的目标的多个时间区域相关联的多个缓冲器 从当前时间点开始读取，每个缓冲器具有存储根据标识符的传送速率确定的数据量的能力，以及将与第二时间区域相对应的缓冲器的大小减小到更小的控制器 比对应于在第二时间区域之前的第一时间区域的缓冲器的大小根据当前时间点和第二时间区域之间的时间差。

公开(公告)号：US20150124836A1

公开(公告)日：2015-05-07

申请号：US14515589

申请日：2014-10-16

Applicant: FUJITSU LIMITED

Inventor： Kazuto NISHIMURA

IPC: H04L12/873

CPC classification number: H04L47/621 ,  H04L47/562 ,  H04L49/3027

Abstract: A communication device includes: a plurality of output ports; a plurality of queues in which packets are stored so as to be sorted into groups of packets that are output from an identical output port in an identical time period, from among the plurality of output ports; a plurality of first selectors that respectively corresponds to the plurality of output ports, and each of which switches a queue from which packets that are output from the output port are read, between the plurality of queues each time the time period elapses; and a second selector that switches a first selector from which packets are output, between the plurality of first selectors, at time intervals in accordance with output rates of packets of the plurality of output ports.

Abstract translation: 通信装置包括：多个输出端口; 多个队列，其中存储分组以从多个输出端口中的相同时间段中从相同的输出端口输出的分组; 分别对应于所述多个输出端口的多个第一选择器，并且每个所述多个第一选择器在每次所述时间段经过之后切换从所述多个队列之间读取从所述输出端口输出的分组的队列; 以及第二选择器，其根据多个输出端口的分组的输出速率，以时间间隔切换在多个第一选择器之间输出分组的第一选择器。

公开(公告)号：US20160308696A1

公开(公告)日：2016-10-20

申请号：US15064953

申请日：2016-03-09

Applicant: FUJITSU LIMITED

Inventor： Kazuto NISHIMURA

IPC: H04L25/20 ,  H04L12/721

CPC classification number: H04L45/38 ,  H04L47/263 ,  H04L47/30 ,  H04L47/6255 ,  H04L47/629

Abstract: An apparatus includes a plurality of first circuits that duplicate and transmit a packet, a memory that store the packet correspond to one of the plurality of first circuit, and a second circuit that select one of the plurality of first circuits, using cumulative remaining copy amount correspond to each of the plurality of first circuits that are calculated based on the packet accumulation in the memory.

Abstract translation: 一种装置包括复制和发送分组的多个第一电路，存储分组对应于多个第一电路中的一个的存储器，以及使用累积剩余拷贝量选择多个第一电路之一的第二电路 对应于基于存储器中的分组累积计算的多个第一电路中的每一个。

公开(公告)号：US20140192819A1

公开(公告)日：2014-07-10

申请号：US14100327

申请日：2013-12-09

Applicant: Fujitsu Limited

Inventor： Kazuto NISHIMURA ,  Atsushi Kitada ,  Hiroshi Tomonaga ,  Tsutomu Noguchi

IPC: H04L12/863

CPC classification number: H04L47/527 ,  H04L47/621 ,  H04L49/206 ,  H04L49/3018 ,  H04L49/505

Abstract: A packet exchanging device includes queues each configured to accumulate one or more packets, a scheduler unit configured to give a certain permissible reading amount indicating amounts of data of readable packets to each of the queues, and a reading processing unit configured to read the one or more packets from the queues by the permissible reading amount in an order in which a reading condition regarding the permissible reading amount for each queue and an amount of data in the one or more packets accumulated in each queue is satisfied.

Abstract translation: 分组交换装置包括每个被配置为累积一个或多个分组的队列;调度器单元，被配置为向每个队列提供指示可读分组数量的一定允许读取量;以及读取处理单元，被配置为读取一个或 来自队列的更多分组按照与每个队列的容许读取量相关的读取条件和每个队列中累积的一个或多个分组中的数据量得到满足的顺序，允许读取量。