公开(公告)号：US20210255830A1

公开(公告)日：2021-08-19

申请号：US16795097

申请日：2020-02-19

Applicant: Facebook, Inc.

Inventor： Thomas Mark Ulrich ,  Abdulkadir Utku Diril ,  Krishnakumar Narayanan Nair ,  Zhao Wang ,  Rakesh Komuravelli

IPC: G06F7/487 ,  G06F7/485

Abstract: A floating-point number in a first format representation is received. Based on an identification of a floating-point format type of the floating-point number, different components of the first format representation are identified. The different components of the first format representation are placed in corresponding components of a second format representation of the floating-point number, wherein a total number of bits of the second format representation is larger than a total number of bits of the first format representation. At least one of the components of the second format representation is padded with one or more zero bits. The floating-point number in the second format representation is stored in a register. A multiplication using the second format representation of the floating-point number is performed.

公开(公告)号：US20210349694A1

公开(公告)日：2021-11-11

申请号：US16869288

申请日：2020-05-07

Applicant: Facebook, Inc.

Inventor： Thomas Mark Ulrich ,  Abdulkadir Utku Diril ,  Zhao Wang

IPC: G06F7/575 ,  G06F7/523 ,  G06F7/483 ,  G06F17/16

Abstract: A device (e.g., integrated circuit chip) includes a first operand register, a second operand register, a multiplication unit, and a hardware logic component. The first operand register is configured to store a first operand value. The second operand register is configured to store a second operand value. The multiplication unit is configured to at least multiply the first operand value with the second operand value. The hardware logic component is configured to detect whether a zero value is provided and in response to a detection that the zero value is being provided: cause an update of at least the first operand register to be disabled, and cause a result of a multiplication of the first operand value with the second operand value to be a zero-value result.

公开(公告)号：US20210319130A1

公开(公告)日：2021-10-14

申请号：US17354957

申请日：2021-06-22

Applicant: Facebook, Inc.

Inventor： Yi Huang ,  Wenlong Dong ,  Marc Alexander Celani ,  Xianliang Zha ,  Yunqing Chen ,  Harikrishna Madadi Reddy ,  Junqiang Lan ,  Chien Cheng Liu ,  Raghuvardhan Moola ,  Haluk Ucar ,  Sujith Srinivasan ,  Handong Li ,  Xing Cindy Chen ,  Tuo Wang ,  Zhao Wang ,  Baheerathan Anandharengan ,  Gaurang Chaudhari ,  Prahlad Rao Venkatapuram ,  Srikanth Alaparthi ,  James Alexander Morle ,  Vincent Matthew Malfa ,  Yassir Azziz ,  Chien-Chung Chen ,  Yan Cui ,  Pedro Eugenio Rocha Pedreira ,  Stavros Harizopoulos

IPC: G06F21/62 ,  G06F16/22 ,  G06F16/901 ,  G06T3/40

Abstract: The disclosed may include various systems and methods for improving the efficiency and scalability of large-scale systems. For example, the disclosed may include systems and methods for automatic privacy enforcement using privacy-aware infrastructure, scalable general-purpose low cost integer motion search, efficient scaler filter coefficients layout for flexible scaling quality control with limited hardware resources, hardware optimization for power saving with both different codecs enabled, optimizing storage overhead and performance for large distributed data warehouse, mass and volume efficient integration of intersatellite link terminals to a satellite bus, and overcoming retention limit for memory-based distributed database systems.