公开(公告)号：US10225069B2

公开(公告)日：2019-03-05

申请号：US15881903

申请日：2018-01-29

Applicant: FUJITSU LIMITED

Inventor： Wahid Rahman ,  Ali Sheikholeslami ,  Takayuki Shibasaki ,  Hirotaka Tamura

IPC: H03L7/08 ,  H04L7/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/099 ,  H04L7/033

Abstract: A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.

公开(公告)号：US20180227114A1

公开(公告)日：2018-08-09

申请号：US15881903

申请日：2018-01-29

Applicant: FUJITSU LIMITED

Inventor： Wahid Rahman ,  Ali Sheikholeslami ,  Takayuki Shibasaki ,  Hirotaka TAMURA

IPC: H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03L7/085

CPC classification number: H04L7/0037 ,  H03L7/0807 ,  H03L7/085 ,  H03L7/087 ,  H03L7/099 ,  H04L7/0079 ,  H04L7/033

Abstract: A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.