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公开(公告)号：US12039233B2
公开(公告)日：2024-07-16
申请号：US17183408
申请日：2021-02-24
Applicant: FUJITSU LIMITED
Inventor： Kouichi Kanda , Hirotaka Tamura
IPC: G06F30/20 , G06F111/06 , G06N10/00
CPC classification number: G06F30/20 , G06N10/00 , G06F2111/06
Abstract: A method includes: accessing first storage configured to store a first weight coefficient group which is at least some of a plurality of weight coefficients indicating a magnitude of interaction between a plurality of state variables in an evaluation function representing energy of an Ising model; accessing a plurality of second storages each of the plurality of second storage being configured to store a second weight coefficient group related to a state variable having a value of 1 in any of a plurality of state variable groups respectively including the plurality of state variables among the plurality of weight coefficients; outputting, for each of the plurality of state variable groups, a search result obtained by performing searching processing configured to perform processing of searching for an optimum solution by repeatedly performing a first update process with a first constraint or a second update process with a second constraint.
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公开(公告)号：US11526740B2
公开(公告)日：2022-12-13
申请号：US16874735
申请日：2020-05-15
Applicant: FUJITSU LIMITED
Inventor： Sanroku Tsukamoto , Hirotaka Tamura , Satoshi Matsubara
Abstract: An optimization method includes holding combining destination information indicating a combining destination neuron to be combined with a target neuron which is one of a plurality of neurons corresponding to a plurality of spins of an Ising model obtained by converting an optimization problem, the target neuron being different in a plurality of neuron circuits; holding a weighting coefficient indicating a strength of combining between the target neuron and the combining destination neuron, and outputting the weighting coefficient corresponding to the combining destination information; permitting an update of a value of the target neuron by using the weighting coefficient output and the value of the update target neuron, and outputting a determination result indicating whether or not the value of the target neuron is permitted to be updated; and determining the update target neuron based on the plurality of determination results respectively output and outputting the update target information.
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公开(公告)号：US11334646B2
公开(公告)日：2022-05-17
申请号：US16795652
申请日：2020-02-20
Applicant: FUJITSU LIMITED
Inventor： Aki Dote , Hirotaka Tamura
IPC: G06F17/11
Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: hold values of a plurality of state variables included in an evaluation function representing energy, and outputs, every certain number of trials, the values of the plurality of state variables; compute, when a state transition occurs in response to changing of one of the values of the plurality of state variables, an energy change value for each state transition based on a weight value selected based on an update index value; and determine a first offset value based on a plurality of the energy change values such that at least one of the state transitions is allowed, outputs a plurality of first evaluation values obtained by adding the first offset value to the plurality of energy change values, and outputs, every certain number of trials, the first offset value.
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公开(公告)号：US11275995B2
公开(公告)日：2022-03-15
申请号：US15609767
申请日：2017-05-31
Applicant: FUJITSU LIMITED
Inventor： Sanroku Tsukamoto , Hirotaka Tamura , Satoshi Matsubara
Abstract: An individual ising device connected to common buses includes neuron circuits, a memory, and a router. The memory holds connection destination information per neuron circuit. An individual item of connection destination information includes first address information identifying one of a plurality of connection destination neuron circuits of a neuron circuit and second address information identifying a first ising device including at least one of the connection destination neuron circuits, the first and second address information being correlated. The router supplies, when an output signal of a connection destination neuron circuit changes and when the router receives the first address information identifying this connection destination neuron circuit via a bus, an update signal based on the changed output signal to one of the neuron circuits in accordance with the received first address information, the previously specified second address information identifying the first ising device, and the connection destination information.
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公开(公告)号：US09213796B2
公开(公告)日：2015-12-15
申请号：US14454539
申请日：2014-08-07
Applicant: FUJITSU LIMITED
Inventor： Hirotaka Tamura , Jason Anderson , Safeen Huda , Hiroaki Fujimoto
IPC: G06F17/50
CPC classification number: G06F17/5077
Abstract: A method for designing a semiconductor integrated circuit includes: determining, by a designing device, first wirings over which signals are propagated and second wirings which are not used for propagation of the signals among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, from among the second wirings, third wirings to be used for storing electrical charges for electrical charge recycling of the first wirings for a most number of the first wirings in a range that satisfies a timing constraint based on operation rates of the signals propagated over the first wirings and delay times of the first wirings.
Abstract translation: 一种半导体集成电路的设计方法，包括：通过设计装置确定传播信号的第一布线和不用于半导体集成电路的多个布线中的信号传播的第二布线; 以及通过所述设计装置从所述第二布线中确定用于在满足基于操作的时间约束的范围内存储用于大量所述第一布线的所述第一布线的电荷再循环的电荷的第三布线 在第一布线和第一布线的延迟时间内传播信号的速率。
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Patent Agency Ranking
公开(公告)号：US08902007B2
公开(公告)日：2014-12-02
申请号：US13706931
申请日：2012-12-06
Applicant: Fujitsu Limited
Inventor： Yasumoto Tomita , Hirotaka Tamura
CPC classification number: H03L7/00 , G06F1/10 , H03K3/0322 , H03L7/0805 , H03L7/099 , H03L7/0995
Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.
Abstract translation: 时钟分配器包括单元电路部件，每个单元电路部件包括振荡器，被配置为将振荡器的输出电压转换为电流的第一元件，具有与第一元件相反相位的电压电流转换特性的第二元件，第二元件 连接到第一元件和振荡器的反馈，被配置为将振荡器的输出电压转换为电流的第三元件，具有与第三元件相反相位的电压电流转换特性的第四元件，第四元件 反馈连接到第三个元件和振荡器; 将单元电路部分的第一和第二元件的连接部分连接到另一单元电路部分的第三和第四元件的连接部分的布线部分; 以及连接到单元电路部分的振荡器的同步电路。
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公开(公告)号：US20130194047A1
公开(公告)日：2013-08-01
申请号：US13706931
申请日：2012-12-06
Applicant: FUJITSU LIMITED
Inventor： Yasumoto Tomita , Hirotaka Tamura
IPC: H03L7/00
CPC classification number: H03L7/00 , G06F1/10 , H03K3/0322 , H03L7/0805 , H03L7/099 , H03L7/0995
Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.
Abstract translation: 时钟分配器包括单元电路部件，每个单元电路部件包括振荡器，被配置为将振荡器的输出电压转换为电流的第一元件，具有与第一元件相反相位的电压电流转换特性的第二元件，第二元件 连接到第一元件和振荡器的反馈，被配置为将振荡器的输出电压转换成电流的第三元件，具有与第三元件相反相位的电压电流转换特性的第四元件，第四元件是 反馈连接到第三个元件和振荡器; 将单元电路部分的第一和第二元件的连接部分连接到另一单元电路部分的第三和第四元件的连接部分的布线部分; 以及连接到单元电路部分的振荡器的同步电路。
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公开(公告)号：US20230315809A1
公开(公告)日：2023-10-05
申请号：US18150422
申请日：2023-01-05
Applicant: Fujitsu Limited
Inventor： Yasuhiro WATANABE , Hirotaka Tamura
IPC: G06F17/18
CPC classification number: G06F17/18
Abstract: A data processing apparatus configured to: search for a combination of values of a plurality of state variables that minimizes or maximizes a value of an Ising-type evaluation function that includes the plurality of state variables, repeat determining whether to permit a change in a value of a first state variable among the plurality of state variables based on the first local field, and when the change in the value of the first state variable is permitted, updating the first local field based on the first weight value, updating the second local field that corresponds to a constraint condition in which the second weight value with the first state variable is non-zero based on the second weight value, and updating the first local field based on the second local field before the updating and the second local field after the updating.
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9.发明公开公开(公告)号：US20230267165A1
公开(公告)日：2023-08-24
申请号：US17980586
申请日：2022-11-04
Applicant: Fujitsu Limited
Inventor： Yasuhiro Watanabe , Hirotaka Tamura
IPC: G06F17/11
CPC classification number: G06F17/11
Abstract: A computer-readable recording medium storing a program for causing a computer of searching for a solution for a combinatorial optimization problem represented by an energy function including state variables, to execute processing including: executing search processing of searching for the solution by performing determination whether or not to accept a change of each value of a plurality of first state variables, for the plurality of first state variables selected from among the state variables in parallel and executing processing of changing the value of one state variable of which the change of the value is determined to be accepted while changing the plurality of selected first state variables; and specifying the number of the plurality of selected first state variables, based on a search status of the search processing or search information that indicates a search record of another combinatorial optimization problem and repeating the search processing.
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公开(公告)号：US11551062B2
公开(公告)日：2023-01-10
申请号：US16240832
申请日：2019-01-07
Applicant: FUJITSU LIMITED
Inventor： Takayuki Shibasaki , Hirotaka Tamura
Abstract: A transition control unit detects, when stochastically determining based on a temperature, energy changes, and a random number whether to accept any of a plurality of state transitions according to a relative relationship between the energy changes and thermal excitation energy, a minimum value among the energy changes. The transition control unit then subtracts, when the minimum value is positive, an offset obtained by multiplying the minimum value by a value M that is greater than 0 and less than or equal to 1 from each of the energy changes corresponding to the plurality of state transitions.
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