公开(公告)号：US09213796B2

公开(公告)日：2015-12-15

申请号：US14454539

申请日：2014-08-07

Applicant: FUJITSU LIMITED

Inventor： Hirotaka Tamura ,  Jason Anderson ,  Safeen Huda ,  Hiroaki Fujimoto

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method for designing a semiconductor integrated circuit includes: determining, by a designing device, first wirings over which signals are propagated and second wirings which are not used for propagation of the signals among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, from among the second wirings, third wirings to be used for storing electrical charges for electrical charge recycling of the first wirings for a most number of the first wirings in a range that satisfies a timing constraint based on operation rates of the signals propagated over the first wirings and delay times of the first wirings.

Abstract translation: 一种半导体集成电路的设计方法，包括：通过设计装置确定传播信号的第一布线和不用于半导体集成电路的多个布线中的信号传播的第二布线; 以及通过所述设计装置从所述第二布线中确定用于在满足基于操作的时间约束的范围内存储用于大量所述第一布线的所述第一布线的电荷再循环的电荷的第三布线 在第一布线和第一布线的延迟时间内传播信号的速率。

公开(公告)号：US09742405B2

公开(公告)日：2017-08-22

申请号：US14339509

申请日：2014-07-24

Applicant: FUJITSU LIMITED

Inventor： Hirotaka Tamura ,  Hisanori Fujisawa ,  Hiroaki Fujimoto ,  Safeen Huda ,  Jason Anderson

IPC: H01H47/00 ,  H01H35/00 ,  H01H83/18 ,  H02H3/02 ,  H02H3/42 ,  H03K19/00 ,  G11C5/06 ,  G11C5/14

CPC classification number: H03K19/0019 ,  G11C5/06 ,  G11C5/14 ,  Y10T307/832

Abstract: A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor.

公开(公告)号：US20150067630A1

公开(公告)日：2015-03-05

申请号：US14454539

申请日：2014-08-07

Applicant: FUJITSU LIMITED

Inventor： Hirotaka TAMURA ,  Jason Anderson ,  Safeen Huda ,  Hiroaki Fujimoto

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method for designing a semiconductor integrated circuit includes: determining, by a designing device, a first wiring over which a signal is propagated and a second wiring which is not used for a propagation of the signal among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, the second wiring to be used as a wiring for storing electrical charge for an electrical charge recycling of the first wiring using the most number of the first wiring in a range that satisfies a timing constraint based on an operation rate of the signal propagated over the first wiring and a delay time of the first wiring.

Abstract translation: 一种设计半导体集成电路的方法包括：通过设计装置确定传播信号的第一布线和不用于半导体集成电路的多个布线中的信号传播的第二布线 ; 以及通过所述设计装置，确定要使用第二布线作为用于在满足基于操作的定时约束的范围内使用最多数量的第一布线来存储用于第一布线的电荷再循环的电荷的布线 在第一布线上传播的信号的速率和第一布线的延迟时间。