-
1.发明授权公开(公告)号：US10480934B2
公开(公告)日：2019-11-19
申请号：US16210025
申请日：2018-12-05
申请人： FUJITSU LIMITED
摘要： An apparatus sequentially acquires, from a plurality of reference imaging devices for imaging a silhouette imaged with a base imaging device from viewpoints different from a viewpoint of the base imaging device, silhouette existing position information based on the reference imaging devices, and transforms the silhouette existing position information into a common coordinate system, where the silhouette existing position information indicates an existing position of the silhouette. The apparatus detects a silhouette absence range in which the silhouette does not exist, based on a result of comparison of the silhouette existing position information acquired this time and the silhouette existing position information acquired last time, and searches a range in which the silhouette exists, based on the silhouette absence range.
-
公开(公告)号：US10162795B2
公开(公告)日：2018-12-25
申请号：US15290071
申请日：2016-10-11
申请人： FUJITSU LIMITED
发明人： Masahiko Toichi
摘要： A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.
-
公开(公告)号：US20150003528A1
公开(公告)日：2015-01-01
申请号：US14313279
申请日：2014-06-24
申请人： FUJITSU LIMITED
发明人： Masahiko Toichi
IPC分类号： H04N19/51 , H04N19/583
CPC分类号： H04N19/521 , G06T7/238 , G06T2207/10016 , G06T2207/20016 , H04N19/14 , H04N19/53 , H04N19/57
摘要： An image processing apparatus includes: a memory; and a processor coupled to the memory and configured to: detect, based on a reduced image of a target frame and a reduced image of a reference frame, a first motion vector of a target block divided from the target frame, set a search range including a pixel row in the target frame and parallel to the pixel row corresponding to a first pixel component that is specified by the first motion vector and substantially perpendicular to an edge direction of a block in the reference frame, calculate, for each of second pixel components corresponding to the first pixel component in the search range, an evaluation value representing a difference of a pixel value between the first pixel component and the second pixel component, and correct the first motion vector based on the evaluation value of each of the second pixel components.
摘要翻译： 一种图像处理装置，包括：存储器; 以及处理器，其耦合到所述存储器并且被配置为：基于目标帧的缩小图像和参考帧的缩小图像来检测从所述目标帧划分的目标块的第一运动矢量，设置包括 目标帧中的像素行并且平行于与由第一运动矢量指定并基本上垂直于参考帧中的块的边缘方向的第一像素分量相对应的像素行，针对每个第二像素分量 对应于搜索范围中的第一像素分量的评估值，表示第一像素分量和第二像素分量之间的像素值的差的评估值，并且基于每个第二像素分量的评估值来校正第一运动矢量 。
-
4.发明申请公开(公告)号：US20190195618A1
公开(公告)日：2019-06-27
申请号：US16210025
申请日：2018-12-05
申请人： FUJITSU LIMITED
摘要： An apparatus sequentially acquires, from a plurality of reference imaging devices for imaging a silhouette imaged with a base imaging device from viewpoints different from a viewpoint of the base imaging device, silhouette existing position information based on the reference imaging devices, and transforms the silhouette existing position information into a common coordinate system, where the silhouette existing position information indicates an existing position of the silhouette. The apparatus detects a silhouette absence range in which the silhouette does not exist, based on a result of comparison of the silhouette existing position information acquired this time and the silhouette existing position information acquired last time, and searches a range in which the silhouette exists, based on the silhouette absence range.
-
公开(公告)号：US20170185564A1
公开(公告)日：2017-06-29
申请号：US15290071
申请日：2016-10-11
申请人： FUJITSU LIMITED
发明人： Masahiko Toichi
CPC分类号： G06F15/7875 , G06F9/485 , G06F9/4881 , G06F15/7871
摘要： A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.
-
公开(公告)号：US09748954B2
公开(公告)日：2017-08-29
申请号：US15254413
申请日：2016-09-01
申请人： FUJITSU LIMITED
发明人： Masahiko Toichi
IPC分类号： H03K19/00 , H03K19/177
CPC分类号： H03K19/0008 , H03K19/1776 , H03K19/17784
摘要： A calculation device includes a programmable logic device including a plurality of circuit arrangement areas each to which power supply voltage allowed to be independently controlled is supplied and a calculation circuit coupled to the programmable logic device. The calculation circuit arranges a main circuit that executes specific processing in a first circuit arrangement area included in the plurality of circuit arrangement areas, acquires a second circuit arrangement area in which a sub circuit that executes the specific processing is allowed to be arranged, included in the plurality of circuit arrangement areas and in which the main circuit is not arranged, arranges the sub circuit in the second circuit arrangement area, and causes one of the main circuit and the sub circuit to execute the specific processing.
-
公开(公告)号：US20170117892A1
公开(公告)日：2017-04-27
申请号：US15254413
申请日：2016-09-01
申请人： FUJITSU LIMITED
发明人： Masahiko Toichi
IPC分类号： H03K19/00 , H03K19/177
CPC分类号： H03K19/0008 , H03K19/1776 , H03K19/17784
摘要： A calculation device includes: a programmable logic device including a plurality of circuit arrangement areas each to which power supply voltage allowed to be independently controlled is supplied; and a calculation circuit coupled to the programmable logic device, wherein the calculation circuit: arranges a main circuit that executes specific processing in a first circuit arrangement area included in the plurality of circuit arrangement areas; acquires a second circuit arrangement area in which a sub circuit that executes the specific processing is allowed to be arranged, included in the plurality of circuit arrangement areas and in which the main circuit is not arranged; arranges the sub circuit in the second circuit arrangement area; and causes one of the main circuit and the sub circuit to execute the specific processing.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.012 秒)
