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公开(公告)号：US20180184514A1
公开(公告)日：2018-06-28
申请号：US15807648
申请日：2017-11-09
Applicant: FUJITSU LIMITED
Inventor： Tetsuro Yamada , AKIKO MATSUI , Mitsuhiko Sugane , Takahide Mukoyama , YOSHIYUKI HIROSHIMA , Kohei Choraku
IPC: H05K1/02 , H05K1/18 , H05K1/11 , H01L23/498 , H01L23/00
CPC classification number: H05K1/0213 , H01L23/49816 , H01L24/16 , H01L2224/16235 , H01L2924/15311 , H05K1/0265 , H05K1/113 , H05K1/115 , H05K1/116 , H05K1/181 , H05K2201/09463 , H05K2201/09609 , H05K2201/0979 , H05K2201/10378 , H05K2201/10734
Abstract: A printed circuit board includes a power feeding layer to which a power supply voltage is applied, a plurality of power feeding terminals that is disposed in an area, in which an electronic component is mounted, and supplies current based on the power supply voltage to the electronic component, and a plurality of vias that electrically interconnects the plurality of power feeding terminals and the power feeding layer, and is formed such that a via coupled to a power feeding terminal disposed closer to an end of the area has a smaller via-diameter.
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公开(公告)号：US20190220564A1
公开(公告)日：2019-07-18
申请号：US16239978
申请日：2019-01-04
Applicant: FUJITSU LIMITED
Inventor： Mitsunori ABE , YOSHIYUKI HIROSHIMA , Takahiro KITAGAWA , Naoki NAKAMURA , AKIKO MATSUI
CPC classification number: G06F17/5036 , G01R31/2817 , H05K1/115 , H05K3/0005
Abstract: A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, Δε={(L×α×Δt×E)/(D×T)}×m, where Δε is the amount of distortion, L is a length of the via, α is a thermal expansion coefficient of a base material, Δt is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n×365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression Nx=C/Δε.
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3.发明申请公开(公告)号：US20180156993A1
公开(公告)日：2018-06-07
申请号：US15813191
申请日：2017-11-15
Applicant: FUJITSU LIMITED
Inventor： YOSHIYUKI HIROSHIMA , AKIKO MATSUI , Mitsuhiko Sugane , Takahide Mukoyama , Tetsuro Yamada , Kohei Choraku
CPC classification number: G02B6/4245 , G02B6/12002 , G02B6/4214 , G02B6/4221 , G02B6/4238 , G02B6/4239 , G02B6/4246
Abstract: A light emitting element bonded board includes an optical waveguide formed within a board, a hollowed portion in the board, a light emitting element installed in the hollowed portion, and a conductive portion formed in an upper layer and/or a lower layer of the optical waveguide, wherein an optical axis of the light emitting element coincides with a center line of the optical waveguide, and a bonding portion of the light emitting element is bonded to the conductive portion.
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公开(公告)号：US20170290144A1
公开(公告)日：2017-10-05
申请号：US15465895
申请日：2017-03-22
Applicant: FUJITSU LIMITED
Inventor： YOSHIYUKI HIROSHIMA , AKIKO MATSUI , Mitsuhiko Sugane , Takahide Mukoyama , Tetsuro Yamada , Kohei Choraku
CPC classification number: H05K1/0271 , H05K3/0052 , H05K3/043 , H05K3/4644 , H05K2201/09263 , H05K2201/09381 , H05K2201/09418
Abstract: A wiring board manufacturing method includes forming a conductor pattern within a waste board section of a wiring board including a product section and the waste board section, the conductor pattern in which a plurality of polygonal lands made of a conductor are arranged along a first direction and a second direction crossing the first direction, each of the plurality of polygonal lands making contact with an adjacent one of the plurality of polygonal lands at each apex of the plurality of polygonal lands; and selectively removing the conductor at the apex of at least part of the plurality of polygonal lands.
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公开(公告)号：US20200303849A1
公开(公告)日：2020-09-24
申请号：US16894931
申请日：2020-06-08
Applicant: FUJITSU LIMITED
Inventor： Takahide Mukoyama , Tetsuro Yamada , Mitsuhiko Sugane , YOSHIYUKI HIROSHIMA , Kohei Choraku , Kazuki TAKAHASHI , AKIKO MATSUI , Shigeo Iriguchi
Abstract: An electronic component includes: a first terminal that is inserted into a first through hole in a substrate; and a second terminal that is inserted into a second through hole in the substrate, wherein a length of the first terminal from a first end that is inserted into the first through hole to a second end is longer than a length of the second terminal from a third end that is inserted into the second through hole to a fourth end, and a cross sectional area of a portion of the first terminal positioned on a side of the second end with respect to a first joined portion is larger than a cross sectional area of a portion of the second terminal positioned on a side of the fourth end with respect to a second joined portion.
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Patent Agency Ranking
公开(公告)号：US20190324207A1
公开(公告)日：2019-10-24
申请号：US16379333
申请日：2019-04-09
Applicant: FUJITSU LIMITED
Inventor： Kohei Choraku , AKIKO MATSUI , YOSHIYUKI HIROSHIMA , Kazuki TAKAHASHI , Tetsuro Yamada
Abstract: An optical waveguide substrate includes a substrate that includes a recess, a buffer layer disposed on a bottom surface and a wall surface of the recess, and an optical waveguide disposed inside the recess with the buffer layer interposed therebetween and having a cladding layer disposed on the buffer layer and a core layer disposed inside the cladding layer.
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7.发明申请公开(公告)号：US20160202413A1
公开(公告)日：2016-07-14
申请号：US14950981
申请日：2015-11-24
Applicant: FUJITSU LIMITED
Inventor： Kohei Choraku , AKIKO MATSUI , Tetsuro Yamada , YOSHIYUKI HIROSHIMA
CPC classification number: G02B6/12002 , G02B6/12004 , G02B6/125 , G02B6/13 , G02B6/42 , G02B6/4214 , G02B6/4224 , G02B6/428 , G02B2006/121 , G02B2006/12104 , G02B2006/12121 , G02B2006/12123 , G02B2006/12147
Abstract: An optical axis adjustment method for optical interconnection, includes: providing, on a substrate, an optical transmitter including light sources and a mark for acquiring a position of each of the light sources; providing, on the substrate, an optical waveguide including cores each allowing light emitted from the respective light sources to propagate through the core; determining a first position based on the mark as a position of each of the light sources; and forming, at a second position in the optical waveguide corresponding to the first position, first mirrors configured to reflect the light emitted from the respective light sources and make the light propagate through the respective cores.
Abstract translation: 一种用于光互连的光轴调节方法，包括：在基板上提供包括光源的光发射器和用于获取每个光源的位置的标记; 在所述基板上提供包括各自允许从各个光源发射的光传播通过所述芯的芯的光波导; 基于所述标记确定作为每个所述光源的位置的第一位置; 以及在与所述第一位置对应的所述光波导中的第二位置处形成第一反射镜，所述第一反射镜被配置为反射从所述各个光源发射的光，并且使所述光传播通过所述各个核。
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公开(公告)号：US20160192486A1
公开(公告)日：2016-06-30
申请号：US14929502
申请日：2015-11-02
Applicant: FUJITSU LIMITED
Inventor： Mitsuhiko Sugane , AKIKO MATSUI , Takahide Mukoyama , Tetsuro Yamada , YOSHIYUKI HIROSHIMA , Kohei Choraku
CPC classification number: H05K3/4623 , H05K1/0231 , H05K1/0298 , H05K1/162 , H05K3/3436 , H05K3/429
Abstract: A circuit board disclosed herein includes: two substrates opposed to each other, where a dielectric being interposed between the two substrates; a through hole formed in each of the two substrates and filled with the dielectric; a first conductor film formed on an inner surface of the through hole; and a second conductor film covering the through hole on a main surface of each of the two substrates on an opposite side to the dielectric, the second conductor film being connected to the first conductor film on the main surface side.
Abstract translation: 本文公开的电路板包括：彼此相对的两个基板，其中电介质插入在两个基板之间; 形成在两个基板中的每一个中并且填充有电介质的通孔; 形成在所述通孔的内表面上的第一导体膜; 以及第二导电膜，其在与所述电介质相反的一侧覆盖所述两个基板中的每一个的主表面上的所述通孔，所述第二导体膜在所述主表面侧连接到所述第一导体膜。
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公开(公告)号：US20200341042A1
公开(公告)日：2020-10-29
申请号：US16850054
申请日：2020-04-16
Applicant: FUJITSU LIMITED
Inventor： Kazuki TAKAHASHI , AKIKO MATSUI , Kohei Choraku , Mitsunori Abe , Tetsuro Yamada , Yoshio Kobayashi , Sotaro Kobayashi
IPC: G01R27/26
Abstract: A specific conductivity measurement method includes: performing first measurement to obtain a resonance frequency f1 that is outputted to a measuring device when the first and second dielectric flat plates each have a thickness t1, and an unloaded Qu1 that corresponds to the resonance frequency f1; performing second measurement to obtain a resonance frequency f2 that is outputted to the measuring device when the first and second dielectric flat plates each have a thickness t2 that is different from the thickness t1, and an unloaded Qu2 that corresponds to the resonance frequency f2; and calculating a specific conductivity σr of the copper foil and the first and second conductor flat plates based on an arithmetic equation that includes the resonance frequency the unloaded Qu1, the resonance frequency f2, and the unloaded Qu2.
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公开(公告)号：US20200026816A1
公开(公告)日：2020-01-23
申请号：US16502074
申请日：2019-07-03
Applicant: FUJITSU LIMITED
Inventor： Mitsunori Abe , YOSHIYUKI HIROSHIMA , Takahiro KITAGAWA , AKIKO MATSUI , Naoki Nakamura
Abstract: An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, Δε={(L×α×Δt×E)/(D×T)}×m×β×γ×η; calculates a lifetime of the via based on a following equation, M=N/(n×365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.
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