公开(公告)号：US20240021569A1

公开(公告)日：2024-01-18

申请号：US18477635

申请日：2023-09-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yoko NAKAMURA ,  Akihiko IWAYA ,  Mai SAITO ,  Tsubasa WATAKABE

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/31

CPC classification number: H01L24/40 ,  H01L23/3735 ,  H01L23/3107 ,  H01L24/35 ,  H01L2224/40175 ,  H01L2224/4007 ,  H01L2224/352

Abstract: A semiconductor module includes a stacked substrate includes an insulating plate and first and second circuit boards arranged on the insulating plate, a semiconductor element arranged on the first circuit board, and a metal wiring board having a first bonding portion bonded to an upper surface of the semiconductor element via a first bonding material. The first bonding portion includes a first plate-shaped portion that has at a lower surface thereof, a boss protruding toward the semiconductor element, and at an upper surface thereof, a first recess at a position corresponding to a position immediately above the boss and multiple second recesses. At the upper surface of the first plate-shaped portion, each of the second recesses has an opening area smaller than an opening area of the first recess.

公开(公告)号：US20250062271A1

公开(公告)日：2025-02-20

申请号：US18933990

申请日：2024-10-31

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yoko NAKAMURA ,  Akihiko IWAYA ,  Mai SAITO ,  Tsubasa WATAKABE

IPC: H01L23/00 ,  H01L23/373 ,  H01L25/07

Abstract: A semiconductor module, including: a stacked substrate including a plurality of circuit boards formed on an upper surface of an insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The plate-shaped portion has a roughened region in which a plurality of recessed portions are formed on the upper surface of the plate-shaped portion. The plurality of recessed portions include a plurality of first recessed portions that each has a peeling suppressing portion protruding inward to thereby narrow a width of each first recessed portion.

公开(公告)号：US20250054897A1

公开(公告)日：2025-02-13

申请号：US18933720

申请日：2024-10-31

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Mai SAITO ,  Yoko NAKAMURA ,  Tsubasa WATAKABE ,  Akihiko IWAYA

IPC: H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/495 ,  H05K1/02

Abstract: A semiconductor module includes a stacked substrate in which a plurality of circuit boards are arranged on an upper surface of an insulating plate, a semiconductor element arranged on an upper surface of at least one of the circuit boards, and a metal wiring board arranged on an upper surface of the semiconductor element. The metal wiring board has a first bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The first bonding portion includes a plate-shaped portion having an upper surface and a lower surface, and at least one groove is provided along an outer periphery of the first bonding portion on the upper surface of the plate-shaped portion.

公开(公告)号：US20220278039A1

公开(公告)日：2022-09-01

申请号：US17746889

申请日：2022-05-17

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Mai SAITO ,  Akihiko IWAYA ,  Yoko NAKAMURA ,  Tatsuhiko ASAI ,  Hiromichi GOHARA ,  Tsubasa WATAKABE ,  Narumi SATO

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Provided is a semiconductor module including: an insulating circuit board having a circuit pattern formed in one surface; a semiconductor chip placed in the insulating circuit board; and a wiring portion for electrically connecting the semiconductor chip and the circuit pattern. The wiring portion includes a chip connecting portion connected to the semiconductor chip. A surface of the chip connecting portion includes: a plurality of concave portions; and a flat portion disposed between two concave portions.

公开(公告)号：US20250022832A1

公开(公告)日：2025-01-16

申请号：US18902173

申请日：2024-09-30

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tsubasa WATAKABE ,  Akihiko IWAYA ,  Yoko NAKAMURA ,  Yuta TAMAI ,  Mai SAITO

IPC: H01L23/00 ,  H01L23/02 ,  H01L23/31 ,  H01L23/34 ,  H01L23/498

Abstract: A semiconductor module, including: a circuit board including a semiconductor element having an electrode on an upper surface thereof; a lead bonded to the electrode by a bonding material; and a sealing material that seals the semiconductor element and the lead. The lead includes: a bonding portion bonded to the electrode, the bonding portion having a lower surface facing the electrode, and an upper surface opposite to the lower surface, and a plurality of recesses formed on the upper surface of the bonding portion. In a plan view of the semiconductor module, the bonding portion has a plurality of sides, and each recess has a bottom surface of a planar shape, the planar shape having a side extending in a direction that is not orthogonal to any of the sides of the bonding portion. Each of the recesses a barbed portion protruding from a wall surface thereof.

公开(公告)号：US20250062272A1

公开(公告)日：2025-02-20

申请号：US18934226

申请日：2024-10-31

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tsubasa WATAKABE ,  Akihiko IWAYA ,  Yoko NAKAMURA ,  Yuta TAMAI ,  Mai SAITO

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/07 ,  H05K1/14

Abstract: A semiconductor module, including: a stacked substrate, which includes an insulating plate, and a plurality of circuit boards formed on an upper surface of the insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a plate-shaped bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The plate-shaped bonding portion has a plurality of recessed portions formed on an upper surface thereof, each recessed portion is of a hexagonal shape in a plan view of the semiconductor module.

公开(公告)号：US20250054899A1

公开(公告)日：2025-02-13

申请号：US18933883

申请日：2024-10-31

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yuta TAMAI ,  Akihiko IWAYA ,  Mai SAITO ,  Tsubasa WATAKABE ,  Yoko NAKAMURA

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/498

Abstract: A semiconductor module, including: a stacked substrate including a plurality of circuit boards formed on an upper surface of an insulating plate; a semiconductor element formed on an upper surface of one of the plurality of circuit boards; and a metal wiring board formed on an upper surface of the semiconductor element. The metal wiring board has a bonding portion bonded to the upper surface of the semiconductor element via a bonding material. The bonding portion includes a plate-shaped portion having an upper surface and a lower surface. The plate-shaped portion has a roughened region in which a plurality of recessed portions are formed on the upper surface thereof. The plurality of recessed portions include a plurality of kinds, each kind differing in at least one of a size, a shape, and a depth of the recess portions therein from another kind.

公开(公告)号：US20250022833A1

公开(公告)日：2025-01-16

申请号：US18902281

申请日：2024-09-30

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Yoko NAKAMURA ,  Akihiko IWAYA ,  Mai SAITO ,  Tsubasa WATAKABE ,  Yuta TAMAI

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor module, including: a circuit board including a semiconductor element; a lead bonded to an electrode of the semiconductor element by a bonding material; and a sealing material sealing the semiconductor element and the lead. The lead includes: a bonding portion bonded to the electrode, and a roughening recess formed on an upper surface of the bonding portion. The roughening recess includes: a main recess having a first wall surfaces and a second wall surface opposite to each other, and a barbed portion formed on the first wall surface and protruding toward the second wall surface, and a sub-recess having: a center, which is located, in a plan view of the semiconductor module, outside the main recess and at a position away from the first wall surface by a predetermined distance, and an inclined surface that becomes shallower from the center toward an opening end of the main recess.