公开(公告)号：US09568551B1

公开(公告)日：2017-02-14

申请号：US14855396

申请日：2015-09-16

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Sagar Kataria ,  Anurag Jindal ,  Abhishek Mahajan ,  Mayank Parasrampuria

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/318558 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318547 ,  G01R31/318552 ,  G01R31/318572

Abstract: An integrated circuit (IC), operable in internal and external testing modes (INTEST and EXTEST), includes first and second partitions and a functional path therebetween. The first partition includes a first scan chain, a first multiplexer, and a first flip-flop. The second partition includes a second flip-flop and a second scan chain. The first scan chain generates an EXTEST vector initialization signal, based on an EXTEST scan input signal. The first multiplexer receives an INTEST vector initialization signal and the EXTEST vector initialization signal, and generates a scan input signal. The first flip-flop generates a first output signal based on the scan input signal. The functional path provides a second output signal based on the first output signal. The second flip-flop generates a third output signal based on the second output signal. The second scan chain receives the third output signal and generates a test output signal.

Abstract translation: 在内部和外部测试模式（INTEST和EXTEST）中可操作的集成电路（IC）包括第一和第二分区以及它们之间的功能路径。 第一分区包括第一扫描链，第一多路复用器和第一触发器。 第二分区包括第二触发器和第二扫描链。 第一个扫描链基于EXTEST扫描输入信号产生EXTEST矢量初始化信号。 第一多路复用器接收INTEST向量初始化信号和EXTEST向量初始化信号，并产生扫描输入信号。 第一触发器基于扫描输入信号产生第一输出信号。 功能路径基于第一输出信号提供第二输出信号。 第二触发器基于第二输出信号产生第三输出信号。 第二扫描链接收第三输出信号并产生测试输出信号。

公开(公告)号：US09766289B2

公开(公告)日：2017-09-19

申请号：US14875717

申请日：2015-10-06

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Mayank Parasrampuria ,  Anurag Jindal ,  Sagar Kataria

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318385 ,  G01R31/31705 ,  G01R31/318547

Abstract: An integrated circuit (IC) includes a logic built-in self-test (LBIST) system that includes scan chains. The scan chains receive a clock signal and test pattern signals, and generate scan out signals. A debug controller receives the scan out signals and shifts a set of the scan out signals to a joint test action group (JTAG) controller. The debug controller also maintains a dynamic count indicative of the number of debug shift operations performed, and compares the dynamic count with a final count. If the dynamic count is less than the final count, the debug controller performs a second debug shift operation, which facilitates determination of a fault location in the IC.