公开(公告)号：US08037287B2

公开(公告)日：2011-10-11

申请号：US12076165

申请日：2008-03-14

申请人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F9/30

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新 流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联， 这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值 程序指令。 这样可以避免冲洗。

公开(公告)号：US09519538B2

公开(公告)日：2016-12-13

申请号：US13067510

申请日：2011-06-06

申请人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

发明人： Emre Özer ,  Shidhartha Das ,  David Michael Bull

IPC分类号： G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F11/07 ,  G06F9/38

CPC分类号： G06F11/0793 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867 ,  G06F11/0721

摘要： An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.

摘要翻译： 具有与一个或多个流水线级相关联的错误检测和错误恢复电路的指令处理流水线。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 部分错误恢复可能是从指令流水线中刷新上游程序指令。 当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令流水线中刷新。 指令流水线可以另外/替代地设置有与每个信号值相关联的多于一个主存储元件，这些主存储元件以交替方式使用，使得如果信号值被错误地捕获并且需要被修复，则仍然存在 可用主存储元件来适当地捕获与以下程序指令对应的信号值。

公开(公告)号：US07895469B2

公开(公告)日：2011-02-22

申请号：US12285796

申请日：2008-10-14

申请人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

发明人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/00

CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3869

摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.

摘要翻译： 集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗） 基于错误。 流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。 该预测用于触发第二次错误恢复操作（部分流水线停止）。 该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

公开(公告)号：US07979642B2

公开(公告)日：2011-07-12

申请号：US12232188

申请日：2008-09-11

申请人： David Michael Bull ,  Emre Özer

发明人： David Michael Bull ,  Emre Özer

IPC分类号： G06F13/00

CPC分类号： G06F12/126 ,  G06F9/3806 ,  G06F9/3851

摘要： A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item.

摘要翻译： 提供了一种数据处理装置，包括用于执行多个程序线程的处理电路。 至少一个存储单元在多个程序线程之间共享并且包括多个条目，每个条目用于存储与高优先级程序线程或较低优先级程序线程相关联的存储项目。 还提供了用于保存存储单元的多个块中的每一个的历史字段的历史存储器。 在检测到作为对较低优先级存储项目的该条目的分配的结果被从存储单元驱逐的高优先级存储项目时，包含该条目的块的历史字段填充有被驱逐的高优先级存储项目的指示 。 当稍后将高优先级存储项目分配给存储单元的所选条目时，执行所分配的高优先级存储项目与包含所选择的条目的块的历史字段中的指示之间的比较操作，并且在检测到 匹配条件与该条目相关联的锁定指示被设置为禁止进一步驱逐该高优先级存储项目。

公开(公告)号：US08205206B2

公开(公告)日：2012-06-19

申请号：US12149772

申请日：2008-05-08

申请人： Emre Özer ,  Stuart David Biles

发明人： Emre Özer ,  Stuart David Biles

IPC分类号： G06F9/46 ,  G06F13/00

CPC分类号： G06F9/3851 ,  G06F9/5011 ,  G06F2209/5021 ,  G06F2209/507

摘要： A data processing apparatus and method are provided for managing multiple program threads executed by processing circuitry. The multiple program threads include at least one high priority program thread and at least one lower priority program thread. At least one storage unit is shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. Thread control circuitry is used to detect a condition indicating an adverse effect caused by a lower priority program thread being executed by the processing circuitry and resulting from sharing of the at least one storage unit between the multiple program threads. On detection of such a condition, the thread control circuitry issues an alert signal, and a scheduler is then responsive to the alert signal to cause execution of the lower priority program thread causing the adverse effect to be temporarily halted, for example by causing that lower priority program thread to be de-allocated and an alternative lower priority program thread allocated in its place. This has been found to provide a particularly efficient mechanism for allowing any high priority program thread to progress as much as possible, while at the same time improving the overall processor throughput by seeking to find co-operative lower priority program threads.

摘要翻译： 提供了一种用于管理由处理电路执行的多个程序线程的数据处理装置和方法。 多个程序线程包括至少一个高优先级程序线程和至少一个较低优先级的程序线程。 在多个程序线程之间共享至少一个存储单元，并且具有用于存储信息的多个条目，供执行程序线程时由处理电路参考。 线程控制电路用于检测指示由处理电路执行的较低优先级程序线程引起的不利影响的状况，并且由多个程序线程之间的至少一个存储单元的共享产生。 在检测到这种情况时，线程控制电路发出报警信号，并且调度器然后对报警信号作出响应，从而导致低优先级程序线程的执行，从而导致不利影响被暂时停止，例如通过使得较低 要重新分配的优先级程序线程和分配给其的替代低优先级程序线程。 已经发现，这提供了一种特别有效的机制，用于允许任何高优先级的程序线程尽可能地进行，同时通过寻求找到合作的较低优先级的程序线程来提高整体处理器的吞吐量。

公开(公告)号：US09269418B2

公开(公告)日：2016-02-23

申请号：US13366660

申请日：2012-02-06

申请人： Donald Felton ,  Emre Özer ,  Sachin Satish Idgunji

发明人： Donald Felton ,  Emre Özer ,  Sachin Satish Idgunji

IPC分类号： G06F12/14 ,  G11C11/406 ,  G06F21/75 ,  G06F21/79 ,  G11C11/408

CPC分类号： G11C11/40622 ,  G06F21/75 ,  G06F21/79 ,  G11C11/408 ,  G11C2211/4065

摘要： An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.

摘要翻译： 一种装置包括用于存储数据的动态随机存取存储器（DRAM）。 提供刷新控制电路以控制DRAM周期性地执行用于刷新存储在DRAM的每个存储器位置中的数据的刷新周期。 刷新地址序列发生器产生识别在刷新周期期间刷新DRAM的存储器位置的顺序的地址的刷新地址序列。 为了阻止对存储在DRAM中的安全数据的差分功率分析攻击，刷新地址序列以从刷新周期到刷新周期的随机顺序的至少一部分存储器位置的地址生成。

公开(公告)号：US08195886B2

公开(公告)日：2012-06-05

申请号：US11723189

申请日：2007-03-16

申请人： Emre Özer ,  Stuart David Biles

发明人： Emre Özer ,  Stuart David Biles

IPC分类号： G06F12/12

CPC分类号： G06F12/126

摘要： A data processing apparatus and method are provided for implementing a replacement scheme for entries of a storage unit. The data processing apparatus has processing circuitry for executing multiple program threads including at least one high priority program thread and at least one lower priority program thread. A storage unit is then shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. A record is maintained identifying for each entry whether the information stored in that entry is associated with a high priority program thread or a lower priority program thread. Replacement circuitry is then responsive to a predetermined event in order to select a victim entry whose stored information is to be replaced. To achieve this, the replacement circuitry performs a candidate generation operation to identify a plurality of randomly selected candidate entries, and then references the record in order to preferentially select as the victim entry a candidate entry whose stored information is associated with a lower priority program thread. This improves the performance of the high priority program thread(s) by preferentially evicting from the storage unit entries associated with lower priority program threads.

摘要翻译： 提供了一种数据处理装置和方法，用于实现用于存储单元的条目的替换方案。 数据处理装置具有用于执行包括至少一个高优先级程序线程和至少一个较低优先级程序线程的多个程序线程的处理电路。 然后，存储单元在多个程序线程之间共享，并且具有用于存储用于在执行程序线程时由处理电路参考的信息的多个条目。 维护记录以识别每个条目，存储在该条目中的信息是否与高优先级程序线程或较低优先级的程序线程相关联。 然后，替换电路响应于预定事件，以便选择其存储的信息将被替换的受害者条目。 为了实现这一点，替换电路执行候选生成操作以识别多个随机选择的候选条目，然后引用该记录，以优先选择其存储的信息与较低优先级的程序线程相关联的候选条目作为受害者条目 。 这通过优先从与优先级较低的程序线程相关联的存储单元条目中逐出来来提高高优先级程序线程的性能。

公开(公告)号：US07937535B2

公开(公告)日：2011-05-03

申请号：US11709279

申请日：2007-02-22

申请人： Emre Özer ,  Stuart David Biles ,  Simon Andrew Ford

发明人： Emre Özer ,  Stuart David Biles ,  Simon Andrew Ford

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0822 ,  Y02D10/13

摘要： Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.

摘要翻译： 多个处理单元中的每一个具有高速缓存，并且每个高速缓存具有包含段过滤数据的指示电路。 指示电路响应来自相关联的处理单元的访问请求指定的地址以引用段过滤数据，以指示数据是否被明确地不存储或潜在地存储在该段中。 高速缓存一致性电路确保每个处理单元访问的数据是最新的，并且具有其内容源自已经提供的段过滤数据的窥探指示电路。 对于某些访问请求，高速缓存一致性电路发起一致性操作，在此期间，窥探指示电路确定是否有任何缓存需要窥探操作。 对于每个缓存，高速缓存一致性电路向该缓存发出一个通知，用于标识要执行的侦听操作。

公开(公告)号：US09032188B2

公开(公告)日：2015-05-12

申请号：US12078100

申请日：2008-03-27

申请人： Emre Özer ,  Stuart David Biles

发明人： Emre Özer ,  Stuart David Biles

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38 ,  G06F9/48

CPC分类号： G06F9/3851 ,  G06F9/4881

摘要： A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

摘要翻译： 多线程顺序超标量处理器2包括发行阶段12，其包括发行电路22,24，用于根据当前选择的发行策略来选择要发布到执行单元14,16的指令。 多个不同的问题策略由相关联的不同策略电路28,30,32提供，并且策略电路28,30,32的这些实例中的哪一个被选择是由策略选择电路34根据检测到的动态行为 的处理器2。

公开(公告)号：US08732523B2

公开(公告)日：2014-05-20

申请号：US13317593

申请日：2011-10-24

申请人： Emre Özer ,  Yiannakis Sazeides ,  Daniel Kershaw ,  Stuart David Biles

发明人： Emre Özer ,  Yiannakis Sazeides ,  Daniel Kershaw ,  Stuart David Biles

IPC分类号： G06F11/00

CPC分类号： G06F11/1415 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0787 ,  G06F2201/86

摘要： A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.

摘要翻译： 数据处理装置具有驻留在装置内的不同物理位置的多个存储元件，以及故障历史电路，用于检测每个存储元件中发生的局部瞬态故障，并且用于基于检测到的局部瞬态故障来维护全局瞬态故障历史数据。 分析电路监视全局瞬态故障历史数据，以基于预定标准确定全局瞬态故障历史数据是否表示在数据处理装置内发生的随机瞬态故障，或指示协调的瞬时故障攻击。 分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。 这提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图绕过数据处理设备的安全性时发起的协调的瞬态故障攻击。