公开(公告)号：US08791846B2

公开(公告)日：2014-07-29

申请号：US13707135

申请日：2012-12-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young Kyun Cho ,  Jae Ho Jung ,  Kwangchu Lee

IPC: H03M3/00

CPC classification number: H03M3/38 ,  H03M3/384 ,  H03M3/424 ,  H03M3/454

Abstract: When an enable signal representing an offset calibration mode is received, a continuous time delta-sigma modulation apparatus generates a first signal using first and second pulse signals representing outputs of the continuous time delta-sigma modulation apparatus and an operation frequency of the continuous time delta-sigma modulation apparatus, generates first and second output bits by performing a counting operation according to a counting method that is determined according to a pulse signal of first and second comparators, applies a voltage corresponding to the first output bit to a body of a first transistor of a primary integrator, and applies a voltage corresponding to the second output bit to a body of a second transistor of the primary integrator.

Abstract translation: 当接收到表示偏移校准模式的使能信号时，连续时间Δ-Σ调制装置使用表示连续时间Δ-Σ调制装置的输出的第一和第二脉冲信号和连续时间delta的操作频率来产生第一信号 Σ调制装置通过根据根据第一和第二比较器的脉冲信号确定的计数方法执行计数操作来产生第一和第二输出比特，将与第一输出比特相对应的电压施加到第一 晶体管，并且将与第二输出位相对应的电压施加到主积分器的第二晶体管的主体。