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公开(公告)号：US20250077406A1
公开(公告)日：2025-03-06
申请号：US18804853
申请日：2024-08-14
Inventor： Hyun Mi KIM , Chun Gi LYUH
Abstract: Provided is an artificial neural network processing apparatus including: first to fourth submatrix multiplication operators configured to perform a first submatrix multiplication operation and then a second submatrix multiplication operation using eight pieces of input data; a memory mapping unit configured to map at least a portion of the eight pieces of input data to the first to fourth submatrix multiplication operators with a first mapping structure for the first submatrix multiplication operation, and map at least a portion of the eight pieces of input data to the first to fourth submatrix multiplication operators with a second mapping structure for the second submatrix multiplication operation, wherein the first mapping structure and the second mapping structure have different mapping structures; and a controlling unit configured to control the memory mapping unit to be formed with the first mapping structure or the second mapping structure.
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公开(公告)号：US20140348250A1
公开(公告)日：2014-11-27
申请号：US14286822
申请日：2014-05-23
Inventor： Seunghyun CHO , Hyun Mi KIM , Kyung Jin BYUN , Nak Woong EUM
CPC classification number: H04N19/86 , H04N19/423
Abstract: Provided is a method for a plurality of processing elements to filter a plurality of pixel blocks in a plurality of picture partitions for a single frame image. The method for filtering pixel blocks includes: checking the status of a second boundary pixel block adjacent to a picture partition boundary, the second boundary pixel block being one of a plurality of pixel blocks in a second picture partition and neighboring a first boundary pixel block in a first picture partition, the first boundary pixel block neighboring the picture partition boundary; selecting a filtering area for the first boundary pixel block based on the status of the second boundary pixel block; and filtering the filtering area for the first boundary pixel block.
Abstract translation: 提供了一种用于多个处理元件的滤波方法，用于对用于单帧图像的多个图像分区中的多个像素块进行滤波。 用于滤波像素块的方法包括：检查与图像分区边界相邻的第二边界像素块的状态，第二边界像素块是第二图像分区中的多个像素块中的一个，并且邻近第一边界像素块 第一图像分区，与图像分区边界相邻的第一边界像素块; 基于第二边界像素块的状态为第一边界像素块选择滤波区域; 并对第一边界像素块的滤波区域进行滤波。
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公开(公告)号：US20200175355A1
公开(公告)日：2020-06-04
申请号：US16677835
申请日：2019-11-08
Inventor： Jaehoon CHUNG , Young-Su KWON , Chun-Gi LYUH , Chan KIM , Hyun Mi KIM , Jeongmin YANG , Yong Cheol Peter CHO
Abstract: A neural network accelerator in which processing elements are configured in a systolic array structure includes a memory to store a plurality of feature data including first and second feature data and a plurality of kernel data including first and second kernel data, a first processing element to perform an operation based on the first feature data and the first kernel data and output the first feature data, a selection circuit to select one of the first feature data and the second feature data, based on a control signal, and output the selected feature data, a second processing element to perform an operation based on the selected feature data and one of the first and the second kernel data, and a controller to generate the control signal, based on a neural network characteristic associated with the plurality of feature data and kernel data.
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公开(公告)号：US20190164036A1
公开(公告)日：2019-05-30
申请号：US16204499
申请日：2018-11-29
Inventor： Hyun Mi KIM , Young-Su KWON
IPC: G06N3/04
Abstract: A method and an apparatus for generating an address of data for an artificial neural network through steps of: performing an N-dimensional loop operation for generating the address of the data based on predetermined parameters, and generating the address of the data in order according to a predetermined direction are provided.
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公开(公告)号：US20210312281A1
公开(公告)日：2021-10-07
申请号：US17217777
申请日：2021-03-30
Inventor： Hyun Mi KIM
Abstract: An apparatus for automatically generating instructions for an artificial intelligence processor and a method for optimizing the same are provided. The method includes: obtaining a combination of conditions for actions performed by the artificial intelligence processor in consideration of optimization condition information for the actions based on model optimization information that optimizes a neural network model to which the artificial intelligence processor is applied and configuration information of the artificial intelligence processor; generating hardware modeling based on the combination of conditions and predicting a performance value through the hardware modeling; and determining an optimal combination of conditions by comparing the predicted performance value and a preset optimal performance value.
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Patent Agency Ranking
公开(公告)号：US20190220739A1
公开(公告)日：2019-07-18
申请号：US16225729
申请日：2018-12-19
Inventor： Young-Su KWON , Hyun Mi KIM , Jeongmin YANG
Abstract: Provided is a neural network computing device including a neural network memory configured to store input data, a kernel memory configured to store kernel data corresponding to the input data, a kernel data controller configured to determine whether or not a first part of the kernel data matches a predetermined bit string, and if the first part matches the predetermined bit string, configured to generate a plurality of specific data based on a second part of the kernel data, and a neural core configured to perform a first operation between one of the plurality of specific data and the input data.
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公开(公告)号：US20220180192A1
公开(公告)日：2022-06-09
申请号：US17544688
申请日：2021-12-07
Inventor： Hyun Mi KIM
Abstract: A method for optimizing a batch size for an artificial neural network accelerator that processes at least one batch in an apparatus for optimizing a batch size is provided. The method for optimizing a batch size includes: receiving information from an artificial neural network to determine a batch size; and determining the batch size for optimizing basic performance of the artificial neural network according to the artificial neural network.
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公开(公告)号：US20220164192A1
公开(公告)日：2022-05-26
申请号：US17533788
申请日：2021-11-23
Inventor： Chun-Gi LYUH , Hyun Mi KIM , Young-Su KWON , Jin Ho HAN
Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.
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公开(公告)号：US20190079801A1
公开(公告)日：2019-03-14
申请号：US16038243
申请日：2018-07-18
Inventor： Chun-Gi LYUH , Young-Su KWON , Chan KIM , Hyun Mi KIM , Jeongmin YANG , Jaehoon CHUNG , Yong Cheol Peter CHO
Abstract: Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.
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公开(公告)号：US20230177310A1
公开(公告)日：2023-06-08
申请号：US18077111
申请日：2022-12-07
Inventor： Hyun Jeong KWON , Hyun Mi KIM
IPC: G06N3/0442 , G06N3/048
CPC classification number: G06N3/0442 , G06N3/048
Abstract: Proposed is a data parallel processing method for a recurrent neural network in a neural network accelerator based on a systolic array. A data processing device receives voice data of a user in a predetermined time section. The data processing device generates a plurality of voice data units by separating the voice data by sentence. The data processing device generates a plurality of input vectors by vectorizing the plurality of voice data units. The data processing device inputs the plurality of input vectors to a neural network accelerator based on a systolic array. In this manner, the data is processed.
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