公开(公告)号：US20170201259A1

公开(公告)日：2017-07-13

申请号：US15273764

申请日：2016-09-23

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ja Yol LEE ,  Min Jae LEE ,  Cheon Soo KIM ,  Min Uk HEO

IPC: H03L7/099 ,  H03L7/091 ,  H03L7/093 ,  H03L7/18

CPC classification number: H03L7/0991 ,  H03L7/081 ,  H03L7/085 ,  H03L7/091 ,  H03L7/093 ,  H03L7/18 ,  H03L7/183

Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.