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公开(公告)号:US20160335054A1
公开(公告)日:2016-11-17
申请号:US15144771
申请日:2016-05-02
Inventor: Chun Ju YOUN , Joong Seon CHOE , Jong Hoi KIM
CPC classification number: G06F7/588 , G06N99/002 , H04L9/0852
Abstract: A multiple output quantum random number generator coherently measures an optical source noise and outputs a random number sequence based on the independent and coherent measurement of optical source noise. Therefore, it is possible to output a random number sequence at a high speed and to perform multiple outputs.
Abstract translation: 多输出量子随机数发生器相干地测量光源噪声,并基于光源噪声的独立和相干测量输出随机数序列。 因此,可以高速输出随机数序列并执行多个输出。
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公开(公告)号:US20170139162A1
公开(公告)日:2017-05-18
申请号:US15203737
申请日:2016-07-06
Inventor: Young Tak HAN , Sang Ho PARK , Yong Soon BAEK , Jang Uk SHIN , Yong Hwan KWON , Jong Hoi KIM
CPC classification number: G02B6/4224 , G01J1/0209 , G01J1/44 , G01J3/0259 , G01J2001/444 , G02B6/12019 , G02B6/4239 , G02B6/4257 , G02B6/4279 , G02B6/4281 , H04B10/60
Abstract: Provided herein are a multi-channel receiver optical sub-assembly and a manufacturing method thereof. The multi-channel receiver optical sub-assembly includes a PLC chip having a first side into which an optical signal is received and a second side from which the received signal is outputted, with an inclined surface formed on the second side of the PLC chip at a preset angle, a PD carrier bonded onto the PLC chip and made of a glass material, and an SI-PD bonded onto the PD carrier, a lens being integrated therein. The PLC chip, the PD carrier, and the SI-PD are passively aligned by at least one alignment mark and then are bonded.
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公开(公告)号:US20160336368A1
公开(公告)日:2016-11-17
申请号:US15133945
申请日:2016-04-20
Inventor: Seo Young LEE , Young Tak HAN , Jong Hoi KIM , Joong Seon CHOE , Chun Ju YOUN , Hyun Do JUNG
IPC: H01L27/146 , H04B10/60
CPC classification number: H04B10/2504 , G02B6/00 , G02B6/4249 , G02B6/4279
Abstract: There is provided a receiver optical module including a photodetector having a plurality of channels, a capacitor disposing block formed on an upper portion of the photodetector, a plurality of capacitors formed on the capacitor disposing block, and an electrical wiring configured to connect the plurality of capacitors to electrodes of a plurality of channels of the photodetector, wherein the plurality of capacitors are formed on the capacitor disposing block such that distance between the capacitors and the electrodes of the corresponding channels are the same. Distortion and loss of signal characteristics of high frequency can be reduced and quality of a signal can be enhanced.
Abstract translation: 提供了一种接收器光学模块,包括具有多个通道的光电检测器,形成在光电检测器的上部的电容器设置块,形成在电容器设置块上的多个电容器,以及电连接器, 电容器到所述光电检测器的多个通道的电极,其中所述多个电容器形成在所述电容器设置块上,使得所述电容器和相应通道的电极之间的距离相同。 可以降低高频信号特性的失真和损失,提高信号质量。
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公开(公告)号:US20180136419A1
公开(公告)日:2018-05-17
申请号:US15869226
申请日:2018-01-12
Inventor: Young Tak HAN , Sang Ho PARK , Yong Soon BAEK , Jang Uk SHIN , Yong Hwan KWON , Jong Hoi KIM
CPC classification number: G02B6/4224 , G01J1/0209 , G01J1/44 , G01J3/0259 , G01J2001/444 , G02B6/12019 , G02B6/4239 , G02B6/4257 , G02B6/4279 , G02B6/4281 , H04B10/60
Abstract: Provided herein are a multi-channel receiver optical sub-assembly and a manufacturing method thereof. The multi-channel receiver optical sub-assembly includes a PLC chip having a first side into which an optical signal is received and a second side from which the received signal is outputted, with an inclined surface formed on the second side of the PLC chip at a preset angle, a PD carrier bonded onto the PLC chip and made of a glass material, and an SI-PD bonded onto the PD carrier, a lens being integrated therein. The PLC chip, the PD carrier, and the SI-PD are passively aligned by at least one alignment mark and then are bonded.
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公开(公告)号:US20170168371A1
公开(公告)日:2017-06-15
申请号:US15193889
申请日:2016-06-27
Inventor: Duk Jun KIM , Young Ho KO , Dong Young KIM , Won Seok HAN , Yong Hwan KWON , Jong Hoi KIM , Byung Seok CHOI
CPC classification number: G02F1/2257 , G02F2001/212
Abstract: There is provided a method for manufacturing a Mach-Zehnder electrooptic modulator including forming an intrinsic semiconductor layer including a Group III-V compound semiconductor on a Group III-V compound semiconductor substrate having an active region and a passive region, doping a first impurity in the intrinsic semiconductor layer corresponding to the active region to form a core layer disposed on the substrate and undoped with the first impurity and an upper clad layer disposed on the core layer and including a region doped with the first impurity, and patterning the core layer and the upper clad layer.
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