公开(公告)号：US20050111540A1

公开(公告)日：2005-05-26

申请号：US10495941

申请日：2002-10-30

申请人： David Modrie ,  Rob Otte

发明人： David Modrie ,  Rob Otte

IPC分类号： G11B20/10 ,  H04B3/06 ,  H04L7/02 ,  H04L25/03 ,  H03K5/159

CPC分类号： H04L7/0062 ,  G11B20/10009 ,  G11B20/10037 ,  H04L7/0029 ,  H04L7/0079 ,  H04L25/03044 ,  H04L2025/03509 ,  H04L2025/0363

摘要： The invention relates to an LMS-based asynchronous receiver for digital transmission and recording systems. The receiver comprises a digital adaptive equalizer (EQ) for receiving a received sequence rn and for delivering an equalized sequence yn. The equalizer (EQ) operates at the sampling rate 1/Ts, asynchronous to the data rate 1/T. An equalizer adaptation method using LMS techniques is described for adapting equalizer taps asynchronously to the data rate via a control loop. A first sampling rate converter (SRC1) performs timing recovery at the data rate 1/T after equalization on the equalized sequence yn. A second sampling rate converter (SRC2) is provided for converting a delayed version of the received sequence rn into an intermediate control sequence ik at the data rate 1/T.

摘要翻译： 本发明涉及一种用于数字传输和记录系统的基于LMS的异步接收机。 该接收机包括一个数字自适应均衡器（EQ），用于接收一个接收到的序列rn并传送均衡的序列yn。 均衡器（EQ）以与数据速率1 / T异步的采样率1 / Ts工作。 描述了使用LMS技术的均衡器适配方法，用于通过控制回路异步调整均衡器抽头与数据速率。 第一采样率转换器（SRC 1）在均衡序列yn上进行均衡后以数据速率1 / T执行定时恢复。 提供第二采样率转换器（SRC2），用于将接收到的序列rn的延迟版本以数据速率1 / T转换成中间控制序列ik。

公开(公告)号：US07248630B2

公开(公告)日：2007-07-24

申请号：US10495941

申请日：2002-10-30

申请人： David Modrie ,  Rob Otte

发明人： David Modrie ,  Rob Otte

IPC分类号： H03H7/30 ,  H04L27/06

CPC分类号： H04L7/0062 ,  G11B20/10009 ,  G11B20/10037 ,  H04L7/0029 ,  H04L7/0079 ,  H04L25/03044 ,  H04L2025/03509 ,  H04L2025/0363

摘要： The invention relates to an LMS-based asynchronous receiver for digital transmission and recording systems. The receiver comprises a digital adaptive equalizer (EQ) for receiving a received sequence rn and for delivering an equalized sequence yn. The equalizer (EQ) operates at the sampling rate 1/Ts, asynchronous to the data rate 1/T. An equalizer adaptation method using LMS techniques is described for adapting equalizer taps asynchronously to the data rate via a control loop. A first sampling rate converter (SRC1) performs timing recovery at the data rate 1/T after equalization on the equalized sequence yn. A second sampling rate converter (SRC2) is provided for converting a delayed version of the received sequence rn into an intermediate control sequence ik at the data rate 1/T.

摘要翻译： 本发明涉及一种用于数字传输和记录系统的基于LMS的异步接收机。 该接收机包括一个数字自适应均衡器（EQ），用于接收一个接收到的序列rn并传送均衡的序列yn。 均衡器（EQ）以与数据速率1 / T异步的采样率1 / Ts工作。 描述了使用LMS技术的均衡器适配方法，用于通过控制回路异步调整均衡器抽头与数据速率。 第一采样率转换器（SRC 1）在均衡序列yn上进行均衡后以数据速率1 / T执行定时恢复。 提供第二采样率转换器（SRC2），用于将接收到的序列rn的延迟版本以数据速率1 / T转换成中间控制序列ik。

公开(公告)号：US07145945B2

公开(公告)日：2006-12-05

申请号：US10511808

申请日：2003-04-15

申请人： David Modrie ,  Willem Marie Coene

发明人： David Modrie ,  Willem Marie Coene

IPC分类号： H03H7/30 ,  H04L27/06

CPC分类号： H04L25/03038 ,  G11B20/10009 ,  G11B20/1403 ,  G11B2020/1288 ,  G11B2220/2541 ,  H04L7/0062 ,  H04L7/0079 ,  H04L2025/03477 ,  H04L2025/03617

摘要： The invention relates to an interference-free LMS-based asynchronous receiver for digital transmission and recording systems. The receiver, having an asynchronously placed LMS-based adaptive equalizer, has 2 control loops: a timing recovery loop (by means of, for instance a PLL (Phase locked loop) and an equalizer's adaptation loop. Interference between the two loops is avoided by deriving a condition the equalizer should fulfill to avoid the interference between the two loops, which implies “orthogonal control functionality” and by combining the condition with the equalizer's adaptation loop. The equalizer shall adapt so that the condition is always true.

摘要翻译： 本发明涉及一种用于数字传输和记录系统的无干扰的基于LMS的异步接收机。 具有异步放置的基于LMS的自适应均衡器的接收机具有2个控制回路：定时恢复回路（通过例如PLL（锁相环）和均衡器的适配环路），两个回路之间的干扰由 导出均衡器应该达到的条件，以避免两个环路之间的干扰，这意味着“正交控制功能”，并通过将该条件与均衡器的适配环路组合，均衡器应适应条件始终为真。

公开(公告)号：US07263049B2

公开(公告)日：2007-08-28

申请号：US10515465

申请日：2003-04-30

申请人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

发明人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

IPC分类号： G11B5/09

CPC分类号： G11B20/10009 ,  G11B20/1403

摘要： A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means (40) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means (12) for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter (13) converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator (14) for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means (15) for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector (16) for deriving the data sequence (ak) from the equivalent processed sequence (ye),whereby the ratio between the sample rates 1/T and 1/Ts is substantially constant. Conventional synchronous receivers which comprise a Sample Rate Converter have the disadvantage that the digital processing is performed within the control loop of the SRC. The delay resulting from the digital processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are require. Therefore the receiver of the invention does the digital processing outside the control loop. To keep the advantage that the digital processing can be done at a fixed rate, the converting means (40) are controlled by a preset value for keeping the ratio T/Ts constant.

摘要翻译： 描述了用于从模拟信号（Sa）以数据速率1 / T递送数据序列（ak）的接收机，所述接收机包括：a）转换装置，用于通过对模拟信号进行采样来产生接收序列（rn） 信号（Sa），采样率为1 / Ts，由此接收序列（rn）的采样率1 / Ts可由预设值（Pv）控制; b）用于通过处理接收到的序列（rn）来传送经处理的序列（yn）的数字处理装置（12）; c）以数据速率1 / T将处理过的序列（yn）转换为等效处理序列（ye）的第一采样率转换器（13），由等效处理序列（ye）的数据速率由控制 信号（Sc）; d）用于从等效处理序列（ye）传送错误序列（ek）的误差发生器（14）; e）用于根据误差序列（ek）产生控制信号（Sc）的控制信号产生装置（15）; f）用于从等效处理序列（ye）导出数据序列（ak）的检测器（16），由此采样率1 / T和1 / Ts之间的比率基本上是恒定的。 包含采样率转换器的常规同步接收机的缺点在于在SRC的控制环路内进行数字处理。 数字处理造成的延迟有助于环路的整体延迟，这可能导致不稳定性，特别是当需要高带宽时。 因此，本发明的接收机在控制回路外进行数字处理。 为了保持以固定速率进行数字处理的优点，转换装置（40）由预设值控制，以保持比率T / Ts恒定。

公开(公告)号：US20060198467A1

公开(公告)日：2006-09-07

申请号：US10515465

申请日：2003-04-30

申请人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

发明人： David Modrie ,  Koen Vanhoof ,  Aalbert Stek

IPC分类号： H04L27/00

CPC分类号： G11B20/10009 ,  G11B20/1403

摘要： A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means (40) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means (12) for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter (13) for converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator (14) for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means (15) for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector (16) for deriving the data sequence (ak) from the equivalent processed sequence (ye),whereby the ratio between the sample rates 1/T and 1/Ts is substantially constant. Conventional synchronous receivers which comprise a Sample Rate Converter have the disadvantage that the digital processing is performed within the control loop of the SRC. The delay resulting from the digital processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are require. Therefore the receiver of the invention does the digital processing outside the control loop. To keep the advantage that the digital processing can be done at a fixed rate, the converting means (40) are controlled by a preset value for keeping the ratio T/Ts constant.

摘要翻译： 描述了用于从模拟信号（Sa）以数据速率1 / T递送数据序列（ak）的接收机，所述接收机包括：a）转换装置，用于通过对模拟信号进行采样来产生接收序列（rn） 信号（Sa），采样率为1 / Ts，由此接收序列（rn）的采样率1 / Ts可由预设值（Pv）控制; b）用于通过处理接收到的序列（rn）来传送经处理的序列（yn）的数字处理装置（12）; c）用于以数据速率1 / T将处理过的序列（yn）转换为等效处理序列（ye）的第一采样率转换器（13），由此等效处理序列（ye）的数据速率可由 控制信号（Sc）; d）用于从等效处理序列（ye）传送错误序列（ek）的误差发生器（14）; e）用于根据误差序列（ek）产生控制信号（Sc）的控制信号产生装置（15）; f）用于从等效处理序列（ye）导出数据序列（ak）的检测器（16），由此采样率1 / T和1 / Ts之间的比率基本上是恒定的。 包含采样率转换器的常规同步接收机的缺点在于在SRC的控制环路内进行数字处理。 数字处理造成的延迟有助于环路的整体延迟，这可能导致不稳定性，特别是当需要高带宽时。 因此，本发明的接收机在控制回路外进行数字处理。 为了保持以固定速率进行数字处理的优点，转换装置（40）由预设值控制，以保持比率T / Ts恒定。

公开(公告)号：US20070053261A1

公开(公告)日：2007-03-08

申请号：US10539324

申请日：2003-12-02

申请人： Jo Frisson ,  David Modrie

发明人： Jo Frisson ,  David Modrie

IPC分类号： G11B20/10

CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/22

摘要： A device for delivering a data signal at a data rate has crosstalk cancellation. The crosstalk reducing unit (14) has an adaptive filter (15) to generate a crosstalk signal corresponding to a track adjacent to a track being scanned. A subtractor (16) subtracts the crosstalk signal from a read signal. A calculating unit (17) calculates filter coefficients for the adaptive filter. The adaptive filter (15) and subtractor (16) are coupled to an asynchronous clock (18) for operating at an asynchronous sample rate. The crosstalk reducing unit (14) has a sample rate converter (19) coupled to a synchronous clock for converting the output of the subtractor to the data signal (8) at a synchronous sample rate. A timing recovery unit (11) is coupled to the data signal (8) for retrieving the synchronous clock corresponding to the data rate. This has the advantage that the latency introduced by the crosstalk cancellation processing doesn't contribute to the overall delay of the timing recovery loop, while the latter still profits from the crosstalk cancellation.

公开(公告)号：US07218581B2

公开(公告)日：2007-05-15

申请号：US10539324

申请日：2003-12-02

申请人： Jo Stefan Frisson ,  David Modrie

发明人： Jo Stefan Frisson ,  David Modrie

IPC分类号： G11B7/00

CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/22

摘要： A device for delivering a data signal at a data rate has crosstalk cancellation. The crosstalk reducing unit (14) has an adaptive filter (15) to generate a crosstalk signal corresponding to a track adjacent to a track being scanned. A subtractor (16) subtracts the crosstalk signal from a read signal. A calculating unit (17) calculates filter coefficients for the adaptive filter. The adaptive filter (15) and subtractor (16) are coupled to an asynchronous clock (18) for operating at an asynchronous sample rate. The crosstalk reducing unit (14) has a sample rate converter (19) coupled to a synchronous clock for converting the output of the subtractor to the data signal (8) at a synchronous sample rate. A timing recovery unit (11) is coupled to the data signal (8) for retrieving the synchronous clock corresponding to the data rate. This has the advantage that the latency introduced by the crosstalk cancellation processing doesn't contribute to the overall delay of the timing recovery loop, while the latter still profits from the crosstalk cancellation.

摘要翻译： 用于以数据速率传送数据信号的装置具有串扰消除。 串扰降低单元（14）具有自适应滤波器（15），用于产生与被扫描的轨道相邻的轨道相对应的串扰信号。 减法器（16）从读取信号中减去串扰信号。 计算单元（17）计算自适应滤波器的滤波器系数。 自适应滤波器（15）和减法器（16）耦合到用于以异步采样率操作的异步时钟（18）。 串扰降低单元（14）具有耦合到同步时钟的采样率转换器（19），用于以同步采样率将减法器的输出转换为数据信号（8）。 定时恢复单元（11）耦合到数据信号（8），用于检索对应于数据速率的同步时钟。 这具有以下优点：由串扰消除处理引入的延迟对定时恢复循环的总体延迟没有贡献，而后者仍然从串扰消除中获益。

公开(公告)号：US20050175128A1

公开(公告)日：2005-08-11

申请号：US10511808

申请日：2003-04-15

申请人： David Modrie ,  Willem Coene

发明人： David Modrie ,  Willem Coene

IPC分类号： G11B20/10 ,  G11B20/14 ,  H04B3/06 ,  H04L1/00 ,  H04L7/00 ,  H04L7/02 ,  H04L25/03 ,  H04B1/10

CPC分类号： H04L25/03038 ,  G11B20/10009 ,  G11B20/1403 ,  G11B2020/1288 ,  G11B2220/2541 ,  H04L7/0062 ,  H04L7/0079 ,  H04L2025/03477 ,  H04L2025/03617

摘要： The invention relates to an interference-free LMS-based asynchronous receiver for digital transmission and recording systems. The receiver, having an asynchronously placed LMS-based adaptive equalizer, has 2 control loops: a timing recovery loop (by means of, for instance a PLL (Phase locked loop) and an equalizer's adaptation loop. Interference between the two loops is avoided by deriving a condition the equalizer should fulfill to avoid the interference between the two loops, which implies “orthogonal control functionality” and by combining the condition with the equalizer's adaptation loop. The equalizer shall adapt so that the condition is always true.

摘要翻译： 本发明涉及一种用于数字传输和记录系统的无干扰的基于LMS的异步接收机。 具有异步放置的基于LMS的自适应均衡器的接收机具有2个控制回路：定时恢复回路（通过例如PLL（锁相环）和均衡器的适配环路），两个回路之间的干扰由 导出均衡器应该达到的条件，以避免两个环路之间的干扰，这意味着“正交控制功能”，并通过将该条件与均衡器的适配环路组合，均衡器应适应条件始终为真。