公开(公告)号：US5249183A

公开(公告)日：1993-09-28

申请号：US669501

申请日：1991-03-14

申请人： Dave Wong ,  Haim Shafir ,  Joe Heideman ,  Cheng C. Shih

发明人： Dave Wong ,  Haim Shafir ,  Joe Heideman ,  Cheng C. Shih

IPC分类号： H04L12/40 ,  H04L12/413

CPC分类号： H04L12/40182 ,  H04L12/413

摘要： A local area network (LAN) having a 10Base-T media attachment unit (MAU) is disclosed for coupling an attachment unit interface (AUI) to a twisted pair link through an AUI port of the 10Base-T MAU. In addition to meeting or exceeding standards set forth in the proposed supplement (P802.3I/D10) to IEEE standard 802.3 for LANs, the MAU provides an interface between the AUI and a RJ45 (twisted pair) connector which auto-engages when activity is detected on the twisted pair link. Lack of activity on the twisted pair link forces the 10Base-T MAU to isolate its AUI port from the AUI. An Ethernet (coaxial) type MAU commonly connected with the 10Base-T MAU at the AUI may be utilized without manual intervention when the twisted pair link is inactive.

摘要翻译： 公开了具有10Base-T媒体附着单元（MAU）的局域网（LAN），用于通过10Base-T MAU的AUI端口将连接单元接口（AUI）耦合到双绞线链路。 除了满足或超出了针对LAN的IEEE标准802.3的建议补充（P802.3I / D10）中规定的标准之外，MAU还提供AUI和RJ45（双绞线）连接器之间的接口，当接口活动为 在双绞线链路上检测到。 双绞线链路缺乏活动强制10Base-T MAU将其AUI端口与AUI隔离开来。 当双绞线链路处于非活动状态时，可以利用在AUI上与10Base-T MAU通用的以太网（同轴）型MAU，而无需手动干预。

公开(公告)号：US5166635A

公开(公告)日：1992-11-24

申请号：US675648

申请日：1991-03-27

申请人： Cheng C. Shih

发明人： Cheng C. Shih

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/45659 ,  H03F3/3061 ,  H03F3/45192 ,  H03F2203/45398 ,  H03F2203/45402 ,  H03F2203/45418 ,  H03F2203/45508 ,  H03F2203/45722 ,  H03F2203/45732

摘要： A cost-effective, low power and low distortion digital data line driver is disclosed with the capability to operate from a limited voltage source while maintaining wide output voltage swings. The line driver has the noise immunity attribute of a fully differential input device without all the usual complex CMFB circuitry normally required. The line driver provides a low distortion output with a low output impedance and maintains its impedance value on the same order of magnitude at frequencies up to four times the Nyquist rate.

摘要翻译： 公开了一种具有成本效益，低功率和低失真的数字数据线驱动器，其具有从有限的电压源操作的能力，同时保持宽的输出电压摆幅。 线路驱动器具有完全差分输入设备的抗噪声属性，而通常不需要通常的复杂CMFB电路。 线路驱动器提供具有低输出阻抗的低失真输出，并将其阻抗值在高达奈奎斯特速率的四倍的频率下保持在相同的数量级。

公开(公告)号：US5057794A

公开(公告)日：1991-10-15

申请号：US661496

申请日：1991-02-26

申请人： Cheng C. Shih

发明人： Cheng C. Shih

IPC分类号： H03L7/089 ,  H03L7/099

CPC分类号： H03L7/0992 ,  H03L7/089

摘要： An all-digital phase-locked loop (ADPLL) is disclosed having a wide bandwidth while maintaining relatively small steps for phase error correction. A random walk filter with memory and a pattern sensitive phase adjustment circuit cooperate to control the ADPLL frequency/phase adjustment rate by taking multiple, relatively smnall steps in phase error correction at fixed intervals of time. A short cycle occurs when the phase disparity is large, interrupting the execution of the fixed interval cycle expediting the ADPLL phase lock time without sacrificing resolution in the phase error correction steps.

摘要翻译： 公开了具有宽带宽的全数字锁相环（ADPLL），同时维持相对较小的相位误差校正步骤。 具有存储器和模式敏感相位调整电路的随机游走滤波器通过在固定的时间间隔内进行相位误差校正中的多个相对较小的步骤来协调控制ADPLL频率/相位调整率。 当相位差异大时，发生短暂的周期，中断执行固定间隔周期，加快ADPLL锁相时间，而不会牺牲相位误差校正步骤中的分辨率。