公开(公告)号：US20060163640A1

公开(公告)日：2006-07-27

申请号：US11339151

申请日：2006-01-25

申请人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

发明人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

IPC分类号： H01L29/94

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

摘要翻译： 在制造根据该方法制造的金属 - 绝缘体 - 金属（MIM）电容器和金属 - 绝缘体 - 金属（MIM））电容器的方法中，所述方法包括：在半导体衬底上形成绝缘层图案， 层图案具有分别限定要形成电容器单元的区域的多个开口; 在绝缘层图案和半导体衬底上形成下电极导电层; 形成填充所述下电极导电层上的开口的第一牺牲层; 在所述第一牺牲层上形成第二牺牲层; 平面化第二牺牲层; 暴露下电极导电层的上表面; 去除暴露的下电极导电层以形成彼此分离的多个下电极，每个相应于电容器单元; 并且在每个下电极上形成各自对应于电容器单元的电介质层和上电极，以提供构成相同电信号的一个电容器的多个MIM电容器单元。

公开(公告)号：US20060158829A1

公开(公告)日：2006-07-20

申请号：US11335411

申请日：2006-01-19

申请人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

发明人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

IPC分类号： H01G4/20

CPC分类号： H01G4/10 ,  H01G4/20

摘要： Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

公开(公告)号：US07732296B2

公开(公告)日：2010-06-08

申请号：US11339151

申请日：2006-01-25

申请人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

发明人： Jung-min Park ,  Seok-jun Won ,  Min-woo Song ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Weon-hong Kim

IPC分类号： H01L21/20

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corresponding to a capacitor cell, on each of the lower electrodes to provide a plurality of MIM capacitor cells constituting one capacitor to which the same electric signal is applied.

摘要翻译： 在制造根据该方法制造的金属 - 绝缘体 - 金属（MIM）电容器和金属 - 绝缘体 - 金属（MIM））电容器的方法中，所述方法包括：在半导体衬底上形成绝缘层图案， 层图案具有分别限定要形成电容器单元的区域的多个开口; 在绝缘层图案和半导体衬底上形成下电极导电层; 形成填充所述下电极导电层上的开口的第一牺牲层; 在所述第一牺牲层上形成第二牺牲层; 平面化第二牺牲层; 暴露下电极导电层的上表面; 去除暴露的下电极导电层以形成彼此分离的多个下电极，每个相应于电容器单元; 并且在每个下电极上形成各自对应于电容器单元的电介质层和上电极，以提供构成相同电信号的一个电容器的多个MIM电容器单元。

公开(公告)号：US07508649B2

公开(公告)日：2009-03-24

申请号：US11335411

申请日：2006-01-19

申请人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

发明人： Dae-jin Kwon ,  Seok-jun Won ,  Weon-hong Kim ,  Yong-kuk Jeong ,  Min-woo Song ,  Jung-min Park

IPC分类号： H01G4/06 ,  H01G4/20

CPC分类号： H01G4/10 ,  H01G4/20

摘要： Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

摘要翻译： 提供了能够提高微电子器件的性能特性的多层电介质膜及其制造方法。 所述多层电介质膜包括由单一成分氧化物构成的单一成分氧化物层，以及复合成分氧化物层，所述复合成分由包含沿所述单一成分氧化物层的任一侧形成的两种以上不同成分的复合成分氧化物构成， 。

公开(公告)号：US07407897B2

公开(公告)日：2008-08-05

申请号：US11173624

申请日：2005-07-01

申请人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L28/65 ,  Y10S438/957

摘要： In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

摘要翻译： 在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。 为了获得这些优点，在​​下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。 下电介质膜和上电介质膜可以由SiO 2组成。 中间电介质膜可以由HFO 2 N 2构成。

公开(公告)号：US20060017136A1

公开(公告)日：2006-01-26

申请号：US11173624

申请日：2005-07-01

申请人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Seok-jun Won ,  Yong-kuk Jeong ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L28/65 ,  Y10S438/957

摘要： In a capacitor of an analog semiconductor device having a multi-layer dielectric film and a method of manufacturing the same, the multi-layer dielectric film can be readily manufactured, has weak reactivity with corresponding electrodes and offers excellent leakage current characteristics. In order to obtain these advantages, a lower dielectric film having a negative quadratic VCC, an intermediate dielectric film having a positive quadratic VCC, and an upper dielectric film having a negative quadratic VCC are sequentially formed between a lower electrode and an upper electrode. The lower dielectric film and the upper dielectric film may be composed of SiO2. The intermediate dielectric film may be composed of HFO2.

摘要翻译： 在具有多层电介质膜的模拟半导体器件的电容器及其制造方法中，可以容易地制造多层电介质膜，与相应的电极具有弱反应性并提供优异的漏电流特性。 为了获得这些优点，在​​下电极和上电极之间顺序地形成具有负二次VCC的下电介质膜，具有正二次VCC的中间电介质膜和具有负二次VCC的上电介质膜。 下电介质膜和上电介质膜可以由SiO 2组成。 中间电介质膜可以由HFO 2 N 2构成。

公开(公告)号：US20060022245A1

公开(公告)日：2006-02-02

申请号：US11187489

申请日：2005-07-22

申请人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  H01L21/02172 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/0805 ,  H01L28/56

摘要： An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.

摘要翻译： 提供了能够减小施加电压对电容的影响的模拟电容器和制造模拟电容器的方法。 模拟电容器包括形成在基板上的下电极，包括至少一个氧化物层和至少一个氧氮化物层的多层电介质层，所述至少一个氧氮化物层由选自Hf，Al，Zr La，Ba，Sr，Ti，Pb，Bi及其组合形成在下电极上，形成在多层电介质层上的上电极。

公开(公告)号：US07679124B2

公开(公告)日：2010-03-16

申请号：US11187489

申请日：2005-07-22

申请人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

发明人： Yong-kuk Jeong ,  Seok-jun Won ,  Dae-jin Kwon ,  Min-woo Song ,  Weon-hong Kim

IPC分类号： H01L27/108

CPC分类号： H01L21/022 ,  H01L21/02172 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/0805 ,  H01L28/56

摘要： An analog capacitor capable of reducing the influence of an applied voltage on a capacitance and a method of manufacturing the analog capacitor are provided. The analog capacitor includes a lower electrode which is formed on a substrate, a multi-layered dielectric layer which includes at least one oxide layer and at least one oxynitride layer which are formed of a material selected from the group consisting of Hf, Al, Zr, La, Ba, Sr, Ti, Pb, Bi and a combination thereof and is formed on the lower electrode, and an upper electrode which is formed on the multi-layered dielectric layer.

摘要翻译： 提供了能够减小施加电压对电容的影响的模拟电容器和制造模拟电容器的方法。 模拟电容器包括形成在基板上的下电极，包括至少一个氧化物层和至少一个氧氮化物层的多层电介质层，所述至少一个氧氮化物层由选自Hf，Al，Zr La，Ba，Sr，Ti，Pb，Bi及其组合形成在下电极上，形成在多层电介质层上的上电极。

公开(公告)号：US07807584B2

公开(公告)日：2010-10-05

申请号：US11812882

申请日：2007-06-22

申请人： Ju-youn Kim ,  Seok-jun Won ,  Weon-hong Kim ,  Min-woo Song ,  Jung-min Park

发明人： Ju-youn Kim ,  Seok-jun Won ,  Weon-hong Kim ,  Min-woo Song ,  Jung-min Park

IPC分类号： H01L21/461

CPC分类号： H01L21/3162 ,  C23C16/45531 ,  C23C16/4554 ,  C23C16/515 ,  C23C16/52 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： Example embodiments are directed to methods of forming a metallic oxide film using Atomic Layer Deposition while controlling the power reflected by a reactor. The method may include feeding metallic source gases, for example, first and second metallic source gases, and/or a reactant gas including oxygen into the reactor individually. One of the metallic source gases may include an amino-group or an alkoxy-group and another metallic source gas may include neither an amino-group nor an alkoxy-group. A plasma may be produced in the reactor from the reactant gas.

摘要翻译： 示例性实施例涉及在控制反应堆反射的功率的同时使用原子层沉积形成金属氧化物膜的方法。 该方法可以包括将金属源气体，例如第一和第二金属源气体和/或包含氧气的反应物气体单独地供入反应器。 金属源气体之一可以包括氨基或烷氧基，而另一种金属源气体既不包括氨基也不包括烷氧基。 可以在反应器中从反应气体中产生等离子体。

公开(公告)号：US20080081409A1

公开(公告)日：2008-04-03

申请号：US11858674

申请日：2007-09-20

申请人： Min-woo Song ,  Seok-jun Won ,  Weon-hong Kim ,  Ju-youn Kim ,  Jung-min Park

发明人： Min-woo Song ,  Seok-jun Won ,  Weon-hong Kim ,  Ju-youn Kim ,  Jung-min Park

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10817 ,  H01L27/10852

摘要： A method of manufacturing a memory device that improves electrical characteristics of an MIM capacitor using a zirconium oxide film (ZrO2) as a dielectric film includes: forming a lower metal electrode on a semiconductor substrate; forming a two or more-layered dielectric film including zirconium oxide films on the lower metal electrode; forming an upper metal electrode on the dielectric film; forming an MIM capacitor by patterning the upper metal electrode, the dielectric film, and the lower metal electrode; forming an interlayer insulating film covering the MIM capacitor; forming contacts in the insulating film; and performing heat treatment at a temperature range of 425 to 500° C.

摘要翻译： 制造使用氧化锆膜（ZrO 2/2）作为电介质膜的MIM电容器的电气特性的存储器件的制造方法包括：在半导体衬底上形成下部金属电极; 在下金属电极上形成包含氧化锆膜的两层或多层电介质膜; 在所述电介质膜上形成上金属电极; 通过图案化上金属电极，电介质膜和下金属电极形成MIM电容器; 形成覆盖所述MIM电容器的层间绝缘膜; 在绝缘膜中形成接触; 并在425〜500℃的温度范围进行热处理。