公开(公告)号：US09319054B2

公开(公告)日：2016-04-19

申请号：US13442262

申请日：2012-04-09

Applicant: Charles A. Webb, III ,  Kishan Shenoi

Inventor： Charles A. Webb, III ,  Kishan Shenoi

IPC: H03L7/197 ,  H04J3/06

CPC classification number: H04J3/0697 ,  H03L7/16 ,  H03L7/1974 ,  H04J3/0661 ,  H04J3/0667

Abstract: Systems and methods are disclosed for utilizing slave (receive) time-stamp clock rates that are different from master (sender) time-stamp clock rates to randomize and thereby reduce systematic time-stamp granularity errors in the communication of network packets. The slave (receive) time-stamp clock rate for some embodiments is set to be a fixed value that has a relationship with the master (sender) time-stamp clock rate such that the ratio of the slave (receive) clock rate to the master (sender) clock rate is a rational number. Other embodiments use a time-varying frequency for the slave (receive) time-stamp clock rate to randomize the slave (receive) time-stamp clock with respect to the master (sender) time-stamp clock. Additional time-stamps can also be generated using a slave (receive) time-stamp clock having a rate set to equal the rate of the master (sender) time-stamp clock signal. Further spread spectrum and/or delta-sigma modulation techniques can be applied to effectively randomize the slave (receive) time-stamp clock.

Abstract translation: 公开了利用与主（发送者）时间标记时钟速率不同的从（接收）时间戳时钟速率来随机化并由此减少网络分组通信中的系统时间戳粒度错误的系统和方法。 一些实施例的从属（接收）时间戳时钟速率被设置为与主（发送者）时间戳时钟速率具有关系的固定值，使得从（接收）时钟速率与主机 （发送者）时钟频率是一个合理的数字。 其他实施例使用从属（接收）时间戳时钟速率的时变频率来相对于主（发送者）时间戳时钟随机化从（接收）时间戳时钟。 也可以使用具有等于主（发送者）时间戳时钟信号的速率的速率的从（接收）时间标记时钟来产生附加的时间戳。 可以应用进一步的扩频和/或Δ-Σ调制技术来有效地使从（接收）时间戳时钟随机化。

公开(公告)号：US20130077642A1

公开(公告)日：2013-03-28

申请号：US13442262

申请日：2012-04-09

Applicant: Charles A. Webb, III ,  Kishan Shenoi

Inventor： Charles A. Webb, III ,  Kishan Shenoi

IPC: H04L7/00

CPC classification number: H04J3/0697 ,  H03L7/16 ,  H03L7/1974 ,  H04J3/0661 ,  H04J3/0667

Abstract: Systems and methods are disclosed for utilizing slave (receive) time-stamp clock rates that are different from master (sender) time-stamp clock rates to randomize and thereby reduce systematic time-stamp granularity errors in the communication of network packets. The slave (receive) time-stamp clock rate for some embodiments is set to be a fixed value that has a relationship with the master (sender) time-stamp clock rate such that the ratio of the slave (receive) clock rate to the master (sender) clock rate is a rational number. Other embodiments use a time-varying frequency for the slave (receive) time-stamp clock rate to randomize the slave (receive) time-stamp clock with respect to the master (sender) time-stamp clock. Additional time-stamps can also be generated using a slave (receive) time-stamp clock having a rate set to equal the rate of the master (sender) time-stamp clock signal. Further spread spectrum and/or delta-sigma modulation techniques can be applied to effectively randomize the slave (receive) time-stamp clock.

Abstract translation: 公开了利用与主（发送者）时间标记时钟速率不同的从（接收）时间戳时钟速率来随机化并由此减少网络分组通信中的系统时间戳粒度错误的系统和方法。 一些实施例的从属（接收）时间戳时钟速率被设置为与主（发送者）时间戳时钟速率具有关系的固定值，使得从（接收）时钟速率与主机 （发送者）时钟频率是一个合理的数字。 其他实施例使用从属（接收）时间戳时钟速率的时变频率来相对于主（发送者）时间戳时钟随机化从（接收）时间戳时钟。 也可以使用具有等于主（发送者）时间戳时钟信号的速率的速率的从（接收）时间标记时钟来产生附加的时间戳。 可以应用进一步的扩频和/或Δ-Σ调制技术来有效地使从（接收）时间戳时钟随机化。

公开(公告)号：US08385212B2

公开(公告)日：2013-02-26

申请号：US12632643

申请日：2009-12-07

Applicant: George P. Zampetti ,  Kishan Shenoi

Inventor： George P. Zampetti ,  Kishan Shenoi

IPC: H04L12/26

CPC classification number: H04L43/0852 ,  H04J3/0682

Abstract: A latency floor between two nodes of a packet-switched network is estimated using transit times of a group of packets traversing the two nodes. In particular, a periodically generated histogram of packet transit times is used to estimate the latency floor. In some packet-switched networks, the behavior of some network elements changes drastically when the network is congested. Because latency floor cannot be accurately estimated under such conditions, packet transit times collected during a congested state of the network are discarded.

Abstract translation: 使用穿过两个节点的一组分组的传送时间来估计分组交换网络的两个节点之间的延迟时间。 特别地，使用周期性地产生的分组传送时间的直方图来估计延迟的底线。 在一些分组交换网络中，当网络拥塞时，一些网络单元的行为发生了巨大的变化。 由于在这种情况下不能准确估计延迟层次，所以在网络拥塞状态期间收集的分组传输时间被丢弃。

公开(公告)号：US20110134766A1

公开(公告)日：2011-06-09

申请号：US12632643

申请日：2009-12-07

Applicant: George P. Zampetti ,  Kishan Shenoi

Inventor： George P. Zampetti ,  Kishan Shenoi

IPC: H04L12/26

CPC classification number: H04L43/0852 ,  H04J3/0682

Abstract: A latency floor between two nodes of a packet-switched network is estimated using transit times of a group of packets traversing the two nodes. In particular, a periodically generated histogram of packet transit times is used to estimate the latency floor. In some packet-switched networks, the behavior of some network elements changes drastically when the network is congested. Because latency floor cannot be accurately estimated under such conditions, packet transit times collected during a congested state of the network are discarded.

Abstract translation: 使用穿过两个节点的一组分组的传送时间来估计分组交换网络的两个节点之间的延迟时间。 特别地，使用周期性地产生的分组传送时间的直方图来估计延迟的底线。 在一些分组交换网络中，当网络拥塞时，一些网络单元的行为发生了巨大的变化。 由于在这种情况下不能准确估计延迟层次，所以在网络拥塞状态期间收集的分组传输时间被丢弃。

公开(公告)号：US07161953B2

公开(公告)日：2007-01-09

申请号：US10156217

申请日：2002-05-28

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: H04J3/16

CPC classification number: H04L12/5601 ,  H04L2012/561 ,  H04L2012/5624 ,  H04L2012/5672

Abstract: Systems and methods are described for bonding multiple G.shdsl links. A method includes transporting digital data including: coupling a first end of a plurality of unbundled network elements to a first modem; coupling a second end of the plurality of unbundled network elements to a second modem; applying a single signal to the first modem; time division multiplexing the single signal into a plurality of signals at the first modem; transmitting the plurality of signals to the second modem over the plurality of unbundled network elements; receiving the plurality of signals at the second modem; and time division demultiplexing the plurality of signals to combine the plurality of signals into a single synchronous signal at the second modem. Each of the plurality of unbundled network elements includes a G.shdsl link.

Abstract translation: 描述了绑定多个G.shdsl链接的系统和方法。 一种方法包括传送数字数据，包括：将多个非捆绑网络元件的第一端耦合到第一调制解调器; 将所述多个非捆绑网络元件的第二端耦合到第二调制解调器; 将单个信号应用于第一调制解调器; 将第一调制解调器的单个信号时分复用为多个信号; 通过所述多个未捆绑的网络单元将所述多个信号发送到所述第二调制解调器; 在第二调制解调器处接收多个信号; 以及对所述多个信号进行时分解复用以将所述多个信号组合成在所述第二调制解调器处的单个同步信号。 多个非捆绑网络元件中的每一个包括G.shdsl链路。

公开(公告)号：US07130332B1

公开(公告)日：2006-10-31

申请号：US09553735

申请日：2000-04-20

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: H04B1/69

CPC classification number: H04B1/70752 ,  H04B1/70754 ,  H04B1/70757 ,  H04B1/7085 ,  H04B2201/70701

Abstract: A method of tracking a pilot channel to discipline an oscillator includes: downconverting the RF signal to a low frequency that is of the order of, but greater than the chip rate; converting the signal into digital format; computing complex correlations between the received digital signal and local replicas of the PN codes; and establishing from the correlation values what is the nominal frequency error of the local oscillator. Correlation values between the digital signal {s(n)} and at least one locally generated version of I-channel and Q-channel PN signals {IPN(n)} and {QPN(n)} are averaged over multiple periods of the PN signals. Pilot signal tracking accuracy is improved, computational load is reduced without degradation in performance, and the technique is simple enough to be incorporated in an off-the-shelf FPGA.

Abstract translation: 跟踪导频信道以对振荡器进行管理的方法包括：将RF信号下变频到大于等于或大于码片速率的低频; 将信号转换成数字格式; 计算接收的数字信号与PN码的本地副本之间的复杂相关; 并从相关值建立本地振荡器的标称频率误差。 数字信号{s（n）和至少一个本地生成的I信道和Q信道PN信号（I和NQ）之间的相关值 （n在PN信号的多个周期上被平均，导频信号跟踪精度提高，计算负载降低而性能下降，并且该技术足够简单，可以并入到现成的FPGA中。

公开(公告)号：US06707329B2

公开(公告)日：2004-03-16

申请号：US10345600

申请日：2003-01-16

Applicant: Kishan Shenoi

Inventor： Kishan Shenoi

IPC: H03L706

CPC classification number: H03L7/089 ,  H03L7/0992 ,  H03L7/0994 ,  H04L7/033 ,  H04L7/0331

Abstract: Systems and method are described for clock recovery or detection of rapid phase transients. An apparatus includes: a numerically controlled oscillator; a phase detector coupled to the numerically controlled oscillator; and a multiplexer coupled to the phase detector and the numerically controlled oscillator, wherein a) the phase detector sets a state variable indicator to either i) a high value when an output phase of the numerically controlled oscillator lags an incoming signal phase, or ii) a low value when the output phase leads the incoming signal phase, b) the multiplexer sends either i) a high increment to the numerically controlled oscillator when the state variable indicator has been set to the high value, or ii) a low increment to the numerically controlled oscillator when the state variable indicator has been set to the low value, and c) the numerically controlled oscillator either i) advances the output phase when the high increment has been sent to the numerically controlled oscillator, or ii) retards the output phase when the low increment has been sent to the numerically controlled oscillator.

Abstract translation: 描述了用于时钟恢复或快速相位瞬变检测的系统和方法。 一种装置包括：数控振荡器; 耦合到数控振荡器的相位检测器; 以及耦合到相位检测器和数控振荡器的多路复用器，其中a）当数控振荡器的输出相位滞后于输入信号相位时，相位检测器将状态变量指示器设置为i）高值，或ii） 当输出相位引导输入信号相位时为低值，b）当状态变量指示器被设置为高值时，多路复用器将i增加到数控振荡器，或者ii）向 数值控制振荡器，当状态变量指示器被设置为低值时，和c）数控振荡器，或者i）当高增量被发送到数控振荡器时，使输出相位前进，或者ii）延迟输出相位 当低增量已经发送到数控振荡器时。

公开(公告)号：US06512803B2

公开(公告)日：2003-01-28

申请号：US09802484

申请日：2001-03-09

Applicant: Johann Heinzl ,  Gary Jacobsen ,  Jining Yang ,  Kishan Shenoi

Inventor： Johann Heinzl ,  Gary Jacobsen ,  Jining Yang ,  Kishan Shenoi

IPC: H04B110

CPC classification number: G01S19/37 ,  G01S19/21 ,  H03J1/0008 ,  H03J3/08 ,  H04B1/7102

Abstract: Systems and methods are described for a GPS receiver capable of functioning in the presence of interference. A method includes detecting an interfering signal including: tuning a band pass filter over a frequency range; and at each of a plurality of incremental frequencies: computing a set of band pass filter coefficients; sending the set of band pass filter coefficients to a digital filter; repeatedly transforming an analog-to-digital converter output having a quantization level in excess of 2 bits into a band pass filter output with the digital filter to obtain a plurality of samples; computing an average of the plurality of samples; and comparing the average to a threshold to detect peaks that exceed a threshold. An apparatus, comprising: an analog radio frequency circuit; an analog-to-digital converter coupled to the analog radio frequency circuit, the analog-to-digital converter providing a quantization level in excess of 2 bits; a digital filter coupled to the analog-to-digital converter; and a digital circuit coupled to the digital filter.

公开(公告)号：US6125125A

公开(公告)日：2000-09-26

申请号：US950429

申请日：1997-10-15

Applicant: Madihally J. Narasimha ,  Kishan Shenoi

Inventor： Madihally J. Narasimha ,  Kishan Shenoi

IPC: H04B7/26 ,  H04J3/06

CPC classification number: H04B7/2693 ,  H04J3/0682

Abstract: New methods for synchronizing previously unsynchronized BTS's of time division multiple access cellular networks are disclosed. Timing information that is readily available throughout the network is used to determine for each BTS when information representing a particular event is transmitted relative to the timing information. The time differences that are detected are used for steering the clock of each BTS to have the next or some other subsequent event transmitted at the same time.

Abstract translation: 公开了用于同步先前未同步的BTS的时分多址蜂窝网络的新方法。 在整个网络中容易获得的定时信息用于为每个BTS确定相对于定时信息发送表示特定事件的信息。 检测到的时间差用于指导每个BTS的时钟，以使下一个或其他后续事件同时发送。

公开(公告)号：US5065395A

公开(公告)日：1991-11-12

申请号：US506678

申请日：1990-04-09

Applicant: Kishan Shenoi ,  Patrick L. Hanagan ,  Helena S. Ho ,  Frank I. Yu

Inventor： Kishan Shenoi ,  Patrick L. Hanagan ,  Helena S. Ho ,  Frank I. Yu

IPC: H04J3/17

CPC classification number: H04J3/172

Abstract: Rudimentary digital speech interpolation apparatus for compressing data on a plurality of channels is disclosed, which includes circuitry for receiving data bits and control bits for each channel. The presence of silence on each channel is determined in response to the received data bits and zero bits are allocated for any silent channel in a frame structure. In addition, circuitry also allocates x bits per channel for the data bits in an non-silent channel in the frame. At least six bits per channel are also allocated for the control bits in the frame. 4N such frames are grouped to form a multi-frame.

Abstract translation: 公开了用于在多个通道上压缩数据的基本数字语音内插装置，其包括用于接收每个通道的数据位和控制位的电路。 响应于接收到的数据位确定每个信道上的静音的存在，并且为帧结构中的任何无声信道分配零位。 此外，电路还为帧中的非静音信道中的数据比特分配每个信道的x比特。 每个通道的至少六位也分配给帧中的控制位。 4N这样的帧被分组以形成多帧。