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公开(公告)号：US10897265B2
公开(公告)日：2021-01-19
申请号：US16682677
申请日：2019-11-13
发明人： Kazuhiro Saito , Hideo Kobayashi , Tetsuya Itano
摘要： An analog-to-digital conversion device of the embodiment includes a comparator and a logic circuit including a switch unit and a logic gate unit that receives a signal output from a comparator. The logic gate unit and the switch unit are connected to each other in series between a power supply node and a ground node.
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公开(公告)号：US20180007297A1
公开(公告)日：2018-01-04
申请号：US15630013
申请日：2017-06-22
IPC分类号： H04N5/378 , H01L27/146 , H03M1/12
CPC分类号： H04N5/378 , H01L27/14634 , H01L27/14636 , H03M1/12 , H03M1/123 , H03M1/56
摘要： A device has stacked first and second substrates. The first substrate includes pixel array having pixels arranged along surface, the second substrate includes readout circuit having first AD-conversion circuit for generating first digital signals corresponding to first signals from the pixels, first parallel-serial conversion circuit for outputting first serial signal by performing parallel-serial conversion on the first digital signals, and processing circuit for processing the first serial signal. In orthogonal projection to the surface, part of the pixel array and part of the processing circuit overlap with each other. The first AD-conversion circuit is arranged between edge of the second substrate and the processing circuit. The first parallel-serial conversion circuit is arranged between the first AD-conversion circuit and the processing circuit.
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公开(公告)号：US09467636B2
公开(公告)日：2016-10-11
申请号：US14043473
申请日：2013-10-01
发明人： Kohichi Nakamura , Koichiro Iwata , Kazuhiro Saito , Takeshi Akiyama , Tetsuya Itano , Hiroki Hiyama , Takashi Muto
IPC分类号： H04N5/335 , H04N5/3745 , H04N5/376 , H04N5/378
CPC分类号： H04N5/37455 , H04N5/37452 , H04N5/3765 , H04N5/378
摘要： A photoelectric conversion device includes a plurality of pixels arranged in a plurality of columns, a plurality of comparators provided correspondingly to the respective columns, a reference signal generation unit configured to supply a reference signal to the plurality of comparators, a counter configured to generate a count signal that includes a plurality of bits in synchronization with a first clock signal, a synchronization unit configured to synchronize the plurality of bits with a second clock signal to generate a synchronized count signal and to output the generated synchronized count signal, and a plurality of memories provided correspondingly to the respective comparators, the memories each being configured to store the synchronized count signal in response to a change in an output of a corresponding one of the comparators.
摘要翻译： 一种光电转换装置，包括以多列排列的多个像素，与各列对应设置的多个比较器，配置为向多个比较器提供基准信号的基准信号生成部，配置为生成 计数信号，其包括与第一时钟信号同步的多个位;同步单元，被配置为使所述多个位与第二时钟信号同步，以产生同步的计数信号并输出所生成的同步计数信号;以及多个 存储器对应于相应的比较器提供，每个存储器被配置为响应于对应的一个比较器的输出的变化来存储同步的计数信号。
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公开(公告)号：US20150237286A1
公开(公告)日：2015-08-20
申请号：US14618143
申请日：2015-02-10
CPC分类号： H04N5/378 , H03M1/34 , H04N5/335 , H04N5/3355 , H04N5/341
摘要： A solid-state imaging apparatus includes: a comparator comparing a signal output from pixels with a reference signal of which level changes dependent on time; a plurality of first bit storage units and a plurality of second bit storage units holding, bit by bit, a count signal of the plurality of bits from a counter, according to a write control signal based on a result of the comparing by the comparator; and a control unit arranged between the comparator and the first and second bit storage units, and adjusting a delay time of the write control signal. An order of lengths of the delay time of the count signal held by the first and second bit storage units is the same as an order of lengths of the delay time of the write control signal of the first and second bit storage units.
摘要翻译： 固态成像装置包括：比较从像素输出的信号与取决于时间的电平变化的参考信号的比较器; 多个第一位存储单元和多个第二位存储单元，根据比较器的比较结果，根据写入控制信号逐位地保存来自计数器的多个位的计数信号; 以及控制单元，布置在比较器与第一和第二位存储单元之间，并且调整写入控制信号的延迟时间。 由第一和第二位存储单元保持的计数信号的延迟时间的长度的顺序与第一和第二位存储单元的写入控制信号的延迟时间的长度的顺序相同。
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公开(公告)号：US20150122975A1
公开(公告)日：2015-05-07
申请号：US14594245
申请日：2015-01-12
发明人： Kazuhiro Saito , Hiroki Hiyama , Tetsuya Itano , Kohichi Nakamura
IPC分类号： H01L27/146
CPC分类号： H04N5/335 , H01L27/14609 , H01L27/14643 , H03M1/1023 , H03M1/123 , H03M1/18 , H03M1/56 , H04N5/357 , H04N5/378
摘要： A solid-state imaging apparatus comprises a plurality of matrix pixels, a reference signal generator for generating a ramp signal, a counter for performing counting according to the ramp signal output, and an AD converter, arranged for each pixel column, for performing AD conversion by comparing a pixel signal from the pixel with the ramp signal. Further, the AD converter includes a comparator to which the pixel signal and the reference signal are input, a storage for storing the AD conversion result, and an slope converter, between the output terminal of the reference signal generator and the input terminal of the comparator, for changing a gradient of the ramp signal, so that the noise overlaid on the ramp signal changes depending on the gradient of the ramp signal. Thus, it is possible to prevent generation of a horizontal-line noise in the ramp signal.
摘要翻译： 固态成像装置包括多个矩阵像素，用于产生斜坡信号的参考信号发生器，用于根据斜坡信号输出执行计数的计数器和针对每个像素列布置的用于执行AD转换的AD转换器 通过比较来自像素的像素信号与斜坡信号。 此外，AD转换器包括输入像素信号和参考信号的比较器，用于存储AD转换结果的存储器和斜率转换器，在参考信号发生器的输出端子和比较器的输入端子之间 ，用于改变斜坡信号的斜率，使得覆盖在斜坡信号上的噪声根据斜坡信号的梯度而改变。 因此，可以防止在斜坡信号中产生水平线噪声。
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6.发明授权Solid-state imaging device and imaging system using buffered counter value of a counter 有权固态成像装置和成像系统使用计数器的缓冲计数器值公开(公告)号：US08848079B2
公开(公告)日：2014-09-30
申请号：US13629332
申请日：2012-09-27
发明人： Tetsuya Itano , Hiroki Hiyama , Kazuhiro Saito , Kohichi Nakamura , Koichiro Iwata , Takeshi Akiyama , Kazuo Yamazaki , Daisuke Yoshida
CPC分类号： H04N5/76 , H04N5/3658 , H04N5/378
摘要： A solid-state imaging device includes a plurality of pixels arranged in a matrix, a plurality of readout circuits provided in each column of the plurality of pixels arranged in a matrix, configured to read out for each column a signal of the plurality of pixels, a plurality of comparison units configured to compare a signal output from the plurality of readout circuits with a reference signal whose level changes with time, a counter configured to perform a count operation from when the level of the reference signal starts to change, first and second buffers each configured to buffer a count value of the counter, and a plurality of storing units connected to the plurality of comparison units, configured to store a count value of the counter when a magnitude relation between a signal output from the plurality of the readout circuits and the reference signal is inverted.
摘要翻译： 固态成像装置包括以矩阵形式排列的多个像素，多个读出电路，设置在以矩阵形式排列的多个像素的每列中，被配置为每列读出多个像素的信号， 多个比较单元，被配置为将来自多个读出电路的信号的输出与其电平随时间变化的参考信号进行比较;配置为在从参考信号的电平开始变化时执行计数操作的计数器;第一和第二 每个被配置为缓冲计数器的计数值的缓冲器和连接到多个比较单元的多个存储单元，被配置为当从多个读出电路输出的信号之间的大小关系时存储计数器的计数值 参考信号反转。
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7.发明申请METHOD FOR DRIVING IMAGING APPARATUS, METHOD FOR DRIVING IMAGING SYSTEM, IMAGING APPARATUS, AND IMAGING SYSTEM 有权驱动成像装置的方法，驱动成像系统的方法，成像装置和成像系统公开(公告)号：US20140063308A1
公开(公告)日：2014-03-06
申请号：US14013294
申请日：2013-08-29
发明人： Kazuhiro Saito
IPC分类号： H04N5/3745
CPC分类号： H04N5/37455 , H04N5/363 , H04N5/3745 , H04N5/378
摘要： A method for driving an imaging apparatus, a method for driving an imaging system, an imaging apparatus, and an imaging system are disclosed in which the number of times of operation which generates digital signals based on an offset component of a comparing circuit is fewer than the number of times of operations which generate digital signals based on photoelectric conversion signals output by a plurality of rows of pixels.
摘要翻译： 公开了用于驱动成像装置的方法，用于驱动成像系统的方法，成像装置和成像系统，其中基于比较电路的偏移分量产生数字信号的操作次数少于 基于由多行像素输出的光电转换信号产生数字信号的操作次数。
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公开(公告)号：US20130089320A1
公开(公告)日：2013-04-11
申请号：US13624183
申请日：2012-09-21
发明人： Hiroki Hiyama , Tetsuya Itano , Kazuhiro Saito , Yu Maehashi , Koichiro Iwata , Kohichi Nakamura
IPC分类号： H04B10/00
CPC分类号： H04N5/37455 , H04N5/378
摘要： A system includes: a plurality of pixels arranged in a matrix; a reference signal generating unit for generating a ramp signal; A/D converters each arranged correspondingly to each of columns to A/D-convert a signal from the pixel; a counter that performs a count operation according to an output of the ramp signal, and supplies the count signal through the count signal line to the A/D converter; and a counter test circuit that is provided independently from the A/D converter, and tests the counter, based on a matching of the expected value of the count signal with the count signal supplied through the count signal line from the counter. This configuration allows the count signal to be checked concurrently with imaging of an object.
摘要翻译： 一种系统包括：以矩阵排列的多个像素; 用于产生斜坡信号的参考信号产生单元; A / D转换器各自相应于每列布置以对来自像素的信号进行A / D转换; 计数器，根据斜坡信号的输出执行计数操作，并通过计数信号线将计数信号提供给A / D转换器; 以及独立于A / D转换器提供的计数器测试电路，并且基于计数信号的期望值与从计数器通过计数信号线提供的计数信号的匹配来测试计数器。 该配置允许在对象的成像的同时检查计数信号。
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9.发明申请RAMP SIGNAL OUTPUT CIRCUIT, ANALOG-TO-DIGITAL CONVERSION CIRCUIT, IMAGING DEVICE, METHOD FOR DRIVING RAMP SIGNAL OUTPUT CIRCUIT, METHOD FOR DRIVING ANALOG-TO-DIGITAL CONVERSION CIRCUIT, AND METHOD FOR DRIVING IMAGING DEVICE 有权RAMP信号输出电路，模拟数字转换电路，成像装置，用于驱动RAMP信号输出电路的方法，用于驱动模拟数字转换电路的方法和驱动成像装置的方法公开(公告)号：US20130087688A1
公开(公告)日：2013-04-11
申请号：US13628365
申请日：2012-09-27
发明人： Kazuhiro Saito , Hiroki Hiyama , Tetsuya Itano , Kohichi Nakamura
IPC分类号： H03K4/06 , H01L27/146
摘要： A circuit configured to output a ramp signal having a potential varying depending on time includes a voltage supply unit configured to supply a plurality of voltages having different amplitudes, a current supply unit, an integration circuit configured to output the ramp signal, and a capacitive element. The voltage supply unit is connected to one terminal of the capacitive element. The integration circuit and the current supply unit are connected to another terminal of the capacitive element.
摘要翻译： 配置为输出具有随时间变化的电位的斜坡信号的电路包括：电压供给单元，被配置为提供具有不同幅度的多个电压;电流供应单元，被配置为输出斜坡信号的积分电路;以及电容元件 。 电压供应单元连接到电容元件的一个端子。 集成电路和电流源单元连接到电容元件的另一个端子。
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10.发明授权公开(公告)号：US11523072B2
公开(公告)日：2022-12-06
申请号：US17103195
申请日：2020-11-24
发明人： Yu Arishima , Kazuhiro Saito
摘要： A photoelectric converter includes pixels, vertical output lines to which a signal is outputted from the pixels, clippers configured to limit a potential of the output lines and a controller. Each of the clippers includes a first circuit configured to output an amplification signal according to a predetermined potential and the potential of the output line and a second circuit configured to supply a current according to the amplification signal to the output line. The controller controls each of the clippers to a state selected from states including a first state in which a range in which the potential of the output line can change is limited using the first and second circuits, and a second state in which the range in which the potential of the vertical output line can change is limited with an output of the second circuit deactivated.
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