公开(公告)号：US20180218999A1

公开(公告)日：2018-08-02

申请号：US15747246

申请日：2016-06-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Paul GONDCHARTON ,  Lamine BENAISSA ,  Bruno IMBERT ,  Guillaume RODRIGUEZ ,  Chiara SABBIONE

IPC: H01L23/00 ,  B81C3/00

CPC classification number: H01L24/83 ,  B81C3/001 ,  H01L21/02002 ,  H01L21/02194 ,  H01L21/02266 ,  H01L21/2007 ,  H01L24/27 ,  H01L2224/2745 ,  H01L2224/80894 ,  H01L2924/0536

Abstract: A bonding between a first substrate and a second substrate, the method includes the steps of: a) providing the first substrate and the second substrate, b) forming a first bonding layer having tungsten oxide on the first substrate and a second bonding layer having tungsten oxide on the second substrate, at least one of the first bonding layer and of the second bonding layer including a third element M so as to form an MWxOy-type alloy, the atomic content of M in the composition of the alloy being between 0.5 and 20% and preferably between 1 and 10%, c) carrying out a direct bonding between the first bonding layer and the second bonding layer, and d) performing a heat treatment at a temperature greater than 250° C.

公开(公告)号：US20240215466A1

公开(公告)日：2024-06-27

申请号：US18393050

申请日：2023-12-21

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Chiara SABBIONE ,  Gabriele NAVARRO ,  Magali TESSAIRE ,  Michel Ranjit FREI ,  Lavinia-Elena NISTOR

IPC: H10N70/00 ,  H10B63/10

CPC classification number: H10N70/8828 ,  H10B63/10

Abstract: A material stack, a microelectronic device that integrates the stack, and a method for obtaining the stack. The material stack for microelectronic device includes a substrate, a first undoped crystalline layer on the substrate, the undoped crystalline layer having a thickness superior to 4 nm, and a Si-doped crystalline chalcogenide layer on the undoped crystalline layer, the Si-doped crystalline chalcogenide layer being doped with less than 20 at. %, and preferably less than 12 at. %, of Si. The provided material stack shows a satisfying stability contributing to retard the stack possible reorganization (i.e., intermixing) that could happen during the manufacturing of the material stack and during the subsequent manufacturing of said microelectronic device.