公开(公告)号：US20140101354A1

公开(公告)日：2014-04-10

申请号：US13647971

申请日：2012-10-09

申请人： Baojing Liu ,  Matt Davidson ,  Aruna Gutta

发明人： Baojing Liu ,  Matt Davidson ,  Aruna Gutta

IPC分类号： G06F13/28

CPC分类号： G06F13/1678 ,  G06F13/1684 ,  G06F13/4018

摘要： First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.

摘要翻译： 第一和第二数据接口提供与多个存储体的数据传输。 第一个数据接口使用第一个总线大小和第一个时钟频率。 第二数据接口使用第二总线大小和第二时钟频率。 第二个总线大小是第一个总线大小的整数倍。 第一个时钟频率是第二个时钟频率的整数倍。 信道化器模块将来自第二数据接口的数据分成第一总线大小的数据段，并使用第一时钟频率将它们发送到多个存储体中的寻址的存储体。 信道化器模块还根据来自多个存储体的第一总线大小和第一时钟频率接收数据，将该数据组合成第二总线大小，并且使用第二时钟频率将数据发送到第二数据接口。

公开(公告)号：US08984203B2

公开(公告)日：2015-03-17

申请号：US13647971

申请日：2012-10-09

申请人： Baojing Liu ,  Matt Davidson ,  Aruna Gutta

发明人： Baojing Liu ,  Matt Davidson ,  Aruna Gutta

IPC分类号： G06F13/38 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F13/1678 ,  G06F13/1684 ,  G06F13/4018

摘要： First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency.

摘要翻译： 第一和第二数据接口提供与多个存储体的数据传输。 第一个数据接口使用第一个总线大小和第一个时钟频率。 第二数据接口使用第二总线大小和第二时钟频率。 第二个总线大小是第一个总线大小的整数倍。 第一个时钟频率是第二个时钟频率的整数倍。 信道化器模块将来自第二数据接口的数据分成第一总线大小的数据段，并使用第一时钟频率将它们发送到多个存储体中的寻址的存储体。 信道化器模块还根据来自多个存储体的第一总线大小和第一时钟频率接收数据，将该数据组合成第二总线大小，并且使用第二时钟频率将数据发送到第二数据接口。

公开(公告)号：US08614584B2

公开(公告)日：2013-12-24

申请号：US13039110

申请日：2011-03-02

申请人： Baojing Liu ,  Aruna Gutta ,  Stephen Skala

发明人： Baojing Liu ,  Aruna Gutta ,  Stephen Skala

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G11C29/022 ,  G01R31/026

摘要： A continuity test circuit for a boundary pad includes a pull-up transistor electrically connected between the boundary pad and a first power supply, and a pull-down transistor electrically connected between the boundary pad and a first reference ground potential. A normal output conductor is electrically connected to have a same electrical state as the boundary pad during normal operation. A continuity test output conductor is electrically connected to have a same electrical state as the boundary pad during continuity test operation. Continuity testing control circuitry is defined to control the pull-up transistor, the pull-down transistor, and the normal output conductor during continuity test operation such that an electrical state present on the continuity test output conductor indicates a status of electrical continuity between the boundary pad and either a second power supply or a second reference ground potential to which the boundary pad should be electrically connected.

摘要翻译： 用于边界焊盘的连续性测试电路包括电连接在边界焊盘和第一电源之间的上拉电晶体，以及电连接在边界焊盘和第一参考接地电位之间的下拉晶体管。 在正常操作期间，正常输出导体电连接以具有与边界焊盘相同的电状态。 连续性测试输出导体在连续性测试操作期间电连接以具有与边界焊盘相同的电状态。 连续性测试控制电路被定义为在连续性测试操作期间控制上拉晶体管，下拉晶体管和正常输出导体，使得存在于导通性测试输出导体上的电状态指示边界之间的电连续性状态 焊盘以及边界焊盘应与其电连接的第二电源或第二参考地电位。

公开(公告)号：US20120223721A1

公开(公告)日：2012-09-06

申请号：US13039110

申请日：2011-03-02

申请人： Baojing Liu ,  Aruna Gutta ,  Stephen Skala

发明人： Baojing Liu ,  Aruna Gutta ,  Stephen Skala

IPC分类号： G01R31/02

CPC分类号： G11C29/022 ,  G01R31/026

摘要： A continuity test circuit for a boundary pad includes a pull-up transistor electrically connected between the boundary pad and a first power supply, and a pull-down transistor electrically connected between the boundary pad and a first reference ground potential. A normal output conductor is electrically connected to have a same electrical state as the boundary pad during normal operation. A continuity test output conductor is electrically connected to have a same electrical state as the boundary pad during continuity test operation. Continuity testing control circuitry is defined to control the pull-up transistor, the pull-down transistor, and the normal output conductor during continuity test operation such that an electrical state present on the continuity test output conductor indicates a status of electrical continuity between the boundary pad and either a second power supply or a second reference ground potential to which the boundary pad should be electrically connected.

摘要翻译： 用于边界焊盘的连续性测试电路包括电连接在边界焊盘和第一电源之间的上拉电晶体，以及电连接在边界焊盘和第一参考接地电位之间的下拉晶体管。 在正常操作期间，正常输出导体电连接以具有与边界焊盘相同的电状态。 连续性测试输出导体在连续性测试操作期间电连接以具有与边界焊盘相同的电状态。 连续性测试控制电路被定义为在连续性测试操作期间控制上拉晶体管，下拉晶体管和正常输出导体，使得存在于导通性测试输出导体上的电状态指示边界之间的电连续性状态 焊盘以及边界焊盘应与其电连接的第二电源或第二参考地电位。

公开(公告)号：US20110246844A1

公开(公告)日：2011-10-06

申请号：US13159311

申请日：2011-06-13

申请人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

发明人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G06F11/267 ,  G01R31/318555

摘要： A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern.

摘要翻译： 软功能触发状态机包括定义为使用扫描波形采样扫描时钟波形以获得采样数据模式的状态机逻辑。 定义状态机逻辑以将采样数据模式与软动作模式进行比较，以确定采样数据模式是否与软操作模式匹配。 当采样数据模式与软动作模式匹配时，状态机逻辑也被定义为触发与软动作模式相关联的动作。

公开(公告)号：US08266485B2

公开(公告)日：2012-09-11

申请号：US13159311

申请日：2011-06-13

申请人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

发明人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/267 ,  G01R31/318555

摘要： A soft-function trigger state machine includes state machine logic defined to use a scan-in waveform to sample a scan-clock waveform to obtain a sampled data pattern. The state machine logic is defined to compare the sampled data pattern to a soft action pattern to determine whether the sampled data pattern matches the soft action pattern. The state machine logic is also defined to trigger an action associated with the soft action pattern when the sampled data pattern matches the soft action pattern.

摘要翻译： 软功能触发状态机包括定义为使用扫描波形采样扫描时钟波形以获得采样数据模式的状态机逻辑。 定义状态机逻辑以将采样数据模式与软动作模式进行比较，以确定采样数据模式是否与软操作模式匹配。 当采样数据模式与软动作模式匹配时，状态机逻辑也被定义为触发与软动作模式相关联的动作。

公开(公告)号：US07962819B2

公开(公告)日：2011-06-14

申请号：US12019534

申请日：2008-01-24

申请人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

发明人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/267 ,  G01R31/318555

摘要： An integrated circuit chip includes a scan-in pin, a scan clock pin, and a test controller. The scan-in pin and the scan clock pin receive a test program for the type of test mode and a soft-reset pattern. A state machine is configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The state machine identifies a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggers a soft reset which eliminates the need for an extra reset pin, when testing in scan mode.

摘要翻译： 集成电路芯片包括扫描引脚，扫描时钟引脚和测试控制器。 扫描引脚和扫描时钟引脚接收测试模式类型和软复位模式的测试程序。 状态机被配置为直接对通过扫描时钟引脚提供的扫描时钟波形进行采样，如通过扫描引脚提供的扫描波形的转换所指示的。 执行软复位模式时，状态机从采样的扫描时钟波形中识别位匹配。 识别的位匹配触发软复位，在扫描模式下进行测试时，无需额外的复位引脚。

公开(公告)号：US20090193305A1

公开(公告)日：2009-07-30

申请号：US12019534

申请日：2008-01-24

申请人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

发明人： Baojing Liu ,  Matt Davidson ,  Vladimir Kovalev

IPC分类号： G01R31/28 ,  G06F11/25

CPC分类号： G06F11/267 ,  G01R31/318555

摘要： An integrated circuit chip having testing logic for testing circuitry of the integrated circuit chip is provided. The integrated circuit chip includes at least a scan-in pin, a scan clock pin, and a test controller. The test controller has test mode registers for storing a type of test mode to be executed, and the test controller accepting signals from the scan-in pin and the scan clock pin. The scan-in pin and the scan clock pin receiving a test program for the type of test mode and a soft-reset pattern. Also included is a state machine logic that is part of the integrated circuit chip. The state machine logic, during execution of the test program, being configured to direct sampling of a scan clock waveform provided through the scan clock pin as dictated by transitions of a scan-in waveform provided through the scan-in pin. The sampling by the state machine circuitry identifying a bit match from the sampled scan clock waveform upon executing the soft-reset pattern. The identified bit match triggering a soft reset by updating the test mode registers of the test controller. The soft reset therefore eliminates the need for an extra reset pin, when testing in scan mode. The communication channel defined through the use of the scan-in and scan clock pins can be used to trigger other soft actions.

摘要翻译： 提供具有用于集成电路芯片的测试电路的测试逻辑的集成电路芯片。 集成电路芯片至少包括扫描引脚，扫描时钟引脚和测试控制器。 测试控制器具有用于存储要执行的测试模式类型的测试模式寄存器，并且测试控制器接受来自扫描引脚和扫描时钟引脚的信号。 扫描引脚和扫描时钟引脚接收测试模式类型的测试程序和软复位模式。 还包括作为集成电路芯片的一部分的状态机逻辑。 在执行测试程序期间，状态机逻辑被配置为直接通过扫描时钟引脚提供的扫描时钟波形的采样，如通过扫描引脚提供的扫描波形的转变所指示的。 在执行软复位模式时，由状态机电路进行采样，从采样的扫描时钟波形中识别位匹配。 所识别的位匹配通过更新测试控制器的测试模式寄存器来触发软复位。 因此，在扫描模式下进行测试时，软复位不需要额外的复位引脚。 通过使用扫描和扫描时钟引脚定义的通信通道可用于触发其他软操作。

公开(公告)号：US07802034B2

公开(公告)日：2010-09-21

申请号：US11618865

申请日：2006-12-31

申请人： Baojing Liu ,  Radhakrishnan Nair ,  Paul Lassa

发明人： Baojing Liu ,  Radhakrishnan Nair ,  Paul Lassa

IPC分类号： G06F13/12 ,  G06F13/38

CPC分类号： G06F13/385

摘要： A USB controller and method of implementing a full transfer automation mode is described. The USB controller may have a host interface module configured to generate hardware logic signals for communication to a backend module having buffer memory. The backend module may be configured to generate hardware logic signals for communication with the host interface module such that data transfer within the USB device may be implemented without the need for processor intervention to handle routing of data packets during a USB bulk data transfer.

摘要翻译： 描述了实现全传输自动化模式的USB控制器和方法。 USB控制器可以具有主机接口模块，其被配置为生成用于与具有缓冲存储器的后端模块通信的硬件逻辑信号。 后端模块可以被配置为生成用于与主机接口模块进行通信的硬件逻辑信号，从而可以实现USB设备内的数据传输，而不需要处理器干预来在USB批量数据传输期间处理数据分组的路由。

公开(公告)号：US20080162737A1

公开(公告)日：2008-07-03

申请号：US11618867

申请日：2006-12-31

申请人： Baojing Liu ,  Radhakrishnan Nair ,  Paul Lassa

发明人： Baojing Liu ,  Radhakrishnan Nair ,  Paul Lassa

IPC分类号： G06F3/06

CPC分类号： G06F3/0658 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/0679 ,  Y02D10/154

摘要： A USB controller and method of implementing a full transfer automation mode is described. The USB controller may have a host interface module configured to generate hardware logic signals for communication to a backend module having buffer memory. The backend module may be configured to generate hardware logic signals for communication with the host interface module such that data transfer within the USB device may be implemented without the need for processor intervention to handle routing of data packets during a USB bulk data transfer.

摘要翻译： 描述了实现全传输自动化模式的USB控制器和方法。 USB控制器可以具有主机接口模块，其被配置为生成用于与具有缓冲存储器的后端模块通信的硬件逻辑信号。 后端模块可以被配置为生成用于与主机接口模块进行通信的硬件逻辑信号，从而可以实现USB设备内的数据传输，而不需要处理器干预来在USB批量数据传输期间处理数据分组的路由。