Abstract:
A system for scalable and predictive packet processing may include a memory and a processor. The memory may be configured to store packet processing results performed on a packet. The processor may be configured to apply the stored packet processing results to subsequently received packets that have the same flow identifier as the processed packet without performing ingress packet processing on the subsequent packets.
Abstract:
A device with dynamically tunable heterogeneous latencies includes an input port configured to receive a packet via a network, and a processing module configured to determine multiple values corresponding to a number of qualifying parameters associated with the packet. The processing module may use the values to generate a selector value and may allocate a latency mode to the packet based on the selector value.