Abstract:
A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.
Abstract:
In the subject system for polarity detection, link initialization between a primary device and a secondary device may be performed in at least two stages, a half-duplex stage when only the primary device transmits initialization signals and any encoded handshaking signals may be set to false, and a full-duplex stage when both devices may transmit initialization signals. The secondary device may perform polarity detection during the half-duplex stage. If the secondary device determines that the polarities of the received signals are reversed, the secondary device may reverse the polarities of any signals subsequently received from, and transmitted to, the primary device. In this manner, the polarities can be corrected for both devices during the half-duplex stage by the secondary device. The secondary device may initiate the full-duplex link initialization stage, during which any handshaking signals may be exchanged, by transmitting signals to the primary device.
Abstract:
A circuit for power on data line (PoDL) injection includes a power source, a first and a second coupling component, and an interface. The power source provides one or more DC voltage levels. The first coupling component couples the power source to an interface for coupling to a transmission medium. An Ethernet device is coupled through the second coupling component to the interface. The first coupling component is a balanced component, and the Ethernet device is isolated from the power source via a pair of DC blocking capacitors connected between the first coupling component and the second coupling component.
Abstract:
In the subject system for remote monitoring and configuration, management of a remote physical layer device may be performed by receiving, at a local physical layer device, an incoming message of a first communication format from a controller device. The incoming message may include a request intended for the remote physical layer device that is communicatively coupled to the local physical layer device over a transmission line carrying a data channel and a supplemental channel. The incoming message may be parsed into an outgoing message of a second communication format for sending to the remote physical layer device through the supplemental channel. The local physical layer device may receive a response from the remote physical layer device through the supplemental channel. The local physical layer device may convert the response from the second communication format into the first communication format for sending the converted response back to the controller device.
Abstract:
A method for frequency synchronization of a multiport device may include recovering a clock frequency of a master port of a first device that is linked to the multiport device at a slave port of the multiport device. A clock frequency of the slave port may be locked to the recovered-clock frequency of the master port of the first device. Frequency data may be stored in a first frequency register associated with the slave port. The stored frequency data may include a difference between the recovered-clock frequency of the master port of the first device and a local-clock frequency of the multiport device. A clock frequency of one or more master ports of the multiport device may be synchronized with the locked clock frequency of the slave port by coupling the first frequency register to frequency registers associated with one or more master ports.