公开(公告)号：US09432038B1

公开(公告)日：2016-08-30

申请号：US14706543

申请日：2015-05-07

Applicant: Broadcom Corporation

Inventor： Christopher Ward ,  Klaas Bult ,  Iniyavan Elumalai

IPC: H03M1/06 ,  H03M1/66 ,  H03K17/16

CPC classification number: H03M1/0604 ,  H03M1/742

Abstract: A semiconductor device fabrication operation is commonly used to manufacture one or more integrated circuits onto a semiconductor substrate. The semiconductor device fabrication operation forms one or more transistors onto an arrangement of fabrication layers to form the one or more integrated circuits which introduces unwanted capacitances, often referred to as parasitic capacitances, into the one or more transistors. The one or more integrated circuits include one or more compensation modules that, when combined with the parasitic capacitances of the one or more transistors, ideally linearizes the non-linearity caused by the parasitic capacitances of the one or more transistors. For example, the one or more compensation modules incorporate a non-linear or a piecewise linear transfer function that is inversely related to the parasitic capacitances of the one or more transistors.

Abstract translation: 半导体器件制造操作通常用于在半导体衬底上制造一个或多个集成电路。 半导体器件制造操作在制造层的布置上形成一个或多个晶体管，以形成将不常用的电容（通常被称为寄生电容）引入到一个或多个晶体管中的一个或多个集成电路。 一个或多个集成电路包括一个或多个补偿模块，当与一个或多个晶体管的寄生电容组合时，理想地线性化由一个或多个晶体管的寄生电容引起的非线性。 例如，一个或多个补偿模块包含与一个或多个晶体管的寄生电容成反比关系的非线性或分段线性传递函数。

公开(公告)号：US20150326111A1

公开(公告)日：2015-11-12

申请号：US14319958

申请日：2014-06-30

Applicant: Broadcom Corporation

Inventor： Scott Savage ,  Stephen Greenwood ,  Christopher Ward ,  Josh Crohn

IPC: H02M3/06 ,  H02M3/155

CPC classification number: H02M3/06 ,  H02M3/155

Abstract: A voltage multiplier circuit. The voltage multiplier circuit includes a storage element, a first transistor, a second transistor and third transistor. The storage element has a first end and a second end. The second end is coupled to a clock signal input. The first transistor has a gate coupled to a voltage node, a first terminal coupled to a supply node, and a second terminal coupled to the first end of the storage element. A second transistor has a first terminal coupled to the first end of the storage element and a second terminal coupled to the voltage output. The third transistor has a gate in communication with the clock input and a first terminal coupled to the voltage node.

Abstract translation: 电压倍增电路。 电压倍增器电路包括存储元件，第一晶体管，第二晶体管和第三晶体管。 存储元件具有第一端和第二端。 第二端耦合到时钟信号输入端。 第一晶体管具有耦合到电压节点的栅极，耦合到电源节点的第一端子和耦合到存储元件的第一端的第二端子。 第二晶体管具有耦合到存储元件的第一端的第一端子和耦合到电压输出的第二端子。 第三晶体管具有与时钟输入通信的栅极和耦合到电压节点的第一端子。

公开(公告)号：US08749410B1

公开(公告)日：2014-06-10

申请号：US13720691

申请日：2012-12-19

Applicant: Broadcom Corporation

Inventor： Frank Van Der Goes ,  Christopher Ward ,  Klaas Bult

IPC: H03M1/06

CPC classification number: H03M1/06 ,  H03M1/1057 ,  H03M1/1215

Abstract: A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.

Abstract translation: 公开了一种多通道模数转换器（ADC），其能够补偿其一个或多个损伤，使得其数字输出准确地表示其模拟输入。 多通道ADC可以补偿多通道ADC使用的采样时钟的多个相位之间的不需要的相位偏移，多通道ADC中的通道之间的不需要的带宽不匹配和/或多通道ADC中的通道之间的不期望的增益失配 -lane ADC提供一些例子。

公开(公告)号：US20140167989A1

公开(公告)日：2014-06-19

申请号：US13720691

申请日：2012-12-19

Applicant: BROADCOM CORPORATION

Inventor： Frank van der GOES ,  Christopher Ward ,  Klaas Bult

IPC: H03M1/06

CPC classification number: H03M1/06 ,  H03M1/1057 ,  H03M1/1215

Abstract: A multi-lane analog-to-digital converter (ADC) is disclosed that is capable of compensating for one or more of its impairments such that its digital output accurately represents its analog input. The multi-lane ADC can compensate for unwanted phase offsets between multiple phases of a sampling clock used by the multi-lane ADC, unwanted bandwidth mismatches between lanes in the multi-lane ADC, and/or unwanted gain mismatches between the lanes in the multi-lane ADC to provide some examples.

Abstract translation: 公开了一种多通道模数转换器（ADC），其能够补偿其一个或多个损伤，使得其数字输出准确地表示其模拟输入。 多通道ADC可以补偿多通道ADC使用的采样时钟的多个相位之间的不需要的相位偏移，多通道ADC中的通道之间的不需要的带宽不匹配和/或多通道ADC中的通道之间的不期望的增益失配 -lane ADC提供一些例子。

公开(公告)号：US09473018B2

公开(公告)日：2016-10-18

申请号：US14319958

申请日：2014-06-30

Applicant: Broadcom Corporation

Inventor： Scott Savage ,  Stephen Greenwood ,  Christopher Ward ,  Josh Crohn

IPC: H03L5/00 ,  H02M3/06 ,  H02M3/155

CPC classification number: H02M3/06 ,  H02M3/155

Abstract: A voltage multiplier circuit. The voltage multiplier circuit includes a storage element, a first transistor, a second transistor and third transistor. The storage element has a first end and a second end. The second end is coupled to a clock signal input. The first transistor has a gate coupled to a voltage node, a first terminal coupled to a supply node, and a second terminal coupled to the first end of the storage element. A second transistor has a first terminal coupled to the first end of the storage element and a second terminal coupled to the voltage output. The third transistor has a gate in communication with the clock input and a first terminal coupled to the voltage node.

Abstract translation: 电压倍增电路。 电压倍增器电路包括存储元件，第一晶体管，第二晶体管和第三晶体管。 存储元件具有第一端和第二端。 第二端耦合到时钟信号输入端。 第一晶体管具有耦合到电压节点的栅极，耦合到电源节点的第一端子和耦合到存储元件的第一端的第二端子。 第二晶体管具有耦合到存储元件的第一端的第一端子和耦合到电压输出的第二端子。 第三晶体管具有与时钟输入通信的栅极和耦合到电压节点的第一端子。