公开(公告)号：US20190057638A1

公开(公告)日：2019-02-21

申请号：US15768948

申请日：2017-10-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha KIM ,  Seung Woo HAN ,  Guangliang SHANG ,  Xing YAO ,  Haoliang ZHENG ,  Mingfu HAN ,  Zhichong WANG ,  Lijun YUAN ,  Yun Sik IM ,  Jing LV ,  Yinglong HUANG ,  Xue DONG

IPC: G09G3/20 ,  G11C19/28

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

公开(公告)号：US20180261177A1

公开(公告)日：2018-09-13

申请号：US15796463

申请日：2017-10-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu HAN ,  Xing YAO ,  Guangliang SHANG ,  Haoliang ZHENG ,  Seung-Woo HAN ,  Jiha KIM ,  Lijun YUAN ,  Zhichong WANG

IPC: G09G3/36 ,  G06F3/041

CPC classification number: G09G3/3677 ,  G06F3/0412 ,  G06F3/0416 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2340/0407 ,  G11C19/28

Abstract: The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.

公开(公告)号：US20190279588A1

公开(公告)日：2019-09-12

申请号：US16066827

申请日：2017-12-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha KIM ,  Lijun YUAN ,  Zhichong WANG ,  Mingfu HAN ,  Xing YAO ,  Guangliang SHANG ,  Seung Woo HAN ,  Yun Sik IM ,  Jing LV ,  Yinglong HUANG ,  Jung Mok JUN ,  Haoliang ZHENG

IPC: G09G3/36 ,  G11C19/28

Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.