DISPLAY MODULE AND METHOD FOR PREPARING SAME, AND DISPLAY DEVICE

    公开(公告)号:US20250107410A1

    公开(公告)日:2025-03-27

    申请号:US18289577

    申请日:2022-12-05

    Abstract: Provided is a display module, including a base substrate, a plurality of light-emitting patterns, and a plurality of microlens groups corresponding to the light-emitting patterns. An orthographic projection region of at least one of the light-emitting patterns on the base substrate forms a primary display region. The plurality of microlens groups are disposed on a side, distal from the base substrate, of the plurality of light-emitting patterns. An orthographic projection of the microlens group on the base substrate is within the primary display region formed by the corresponding light-emitting pattern. The microlens group includes at least two microlens structures, and a gap is defined between any adjacent two microlens structures. The light-emitting pattern includes a target region. An orthographic projection of the target region on the base substrate is overlapped with an orthographic projection of the gap on the base substrate. The target region does not emit light.

    DISPLAY SUBSTRATE AND DISPLAY DEVICE

    公开(公告)号:US20240373674A1

    公开(公告)日:2024-11-07

    申请号:US18031651

    申请日:2022-06-29

    Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate and pixel units each including a pixel driving circuit at least including a first and a second thin film transistors; a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer are sequentially arranged on the base substrate; the first semiconductor layer includes a first active layer, including a first source region, of the first thin film transistor; the first conductive layer includes a first gate of the first thin film transistor; the second conductive layer includes a first transfer electrode electrically connected to the first source region; the second semiconductor layer includes a second active layer, which includes a second source region, of the second thin film transistor; the second source region is electrically connected to the first transfer electrode.

    ARRAY SUBSTRATE, DISPLAY PANEL AND METHOD FOR MANUFACTURING ARRAY SUBSTRATE

    公开(公告)号:US20240395831A1

    公开(公告)日:2024-11-28

    申请号:US18262462

    申请日:2022-09-27

    Abstract: The disclosure relates to an array substrate, a display panel, and a method for manufacturing an array substrate. The array substrate includes a first active layer on a substrate; a second active layer on a side of the first active layer away from the substrate; an intermediate layer between the first and second active layers and including a first via arriving at the first active layer, wherein the second active layer includes first, second and third sub-active layers, the first sub-active layer extending around a perimeter of the first via and in a direction away from the first via, the second sub-active layer covering a side wall of the first via, the third sub-active layer being at a bottom of the first via and covering a portion of a surface of the second active layer exposed by the first via, and wherein the second active layer is continuous.

    DRIVING BACKPLANE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS

    公开(公告)号:US20240347550A1

    公开(公告)日:2024-10-17

    申请号:US18755700

    申请日:2024-06-27

    CPC classification number: H01L27/1251 H01L27/1222 H01L27/124 H01L27/127

    Abstract: A method for preparing a driving backplane includes: providing a base substrate, forming a connecting layer on a side of the base substrate; forming an insulating layer group on a side of the connecting layer away from the base substrate, forming a first via hole by patterning the insulating layer group; forming inducing particles on a side of the insulating layer group away from the base substrate; forming a doped amorphous silicon layer on a side of the inducing particles away from the base substrate, forming a first conductor part by the doped amorphous silicon layer formed in the first via hole, forming a raw material part by patterning the doped amorphous silicon layer; and forming a first channel part by causing the inducing particles to induce the raw material part, wherein the first channel part is connected to the first conductor part.

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