NANOWIRE, FABRICATION METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND ELECTRONIC DEVICE

    公开(公告)号:US20240387631A1

    公开(公告)日:2024-11-21

    申请号:US18273730

    申请日:2022-05-24

    Abstract: The present disclosure provides a nanowire, a fabrication method of an array substrate, an array substrate and an electronic device, belongs to the field of semiconductor technology, and can solve the problem of large area of an active region. The fabrication method of the nanowire includes: forming an insulating layer on a first surface of the substrate; forming a trench layer having a guide trench on a surface of the insulating layer away from the substrate, wherein a width of the guide trench is 0.8 to 1.2 times of a diameter of an induction particle having a specified size; forming the induction particle in the guide trench; forming a precipitation layer on a surface of the trench layer away from the substrate; and forming the nanowire by processing the precipitation layer to separate specified atoms out in the precipitation layer along the guide trench under induction of the induction particle.

    DRIVING BACKPLANE AND PREPARATION METHOD THEREFOR, AND DISPLAY APPARATUS

    公开(公告)号:US20240347550A1

    公开(公告)日:2024-10-17

    申请号:US18755700

    申请日:2024-06-27

    CPC classification number: H01L27/1251 H01L27/1222 H01L27/124 H01L27/127

    Abstract: A method for preparing a driving backplane includes: providing a base substrate, forming a connecting layer on a side of the base substrate; forming an insulating layer group on a side of the connecting layer away from the base substrate, forming a first via hole by patterning the insulating layer group; forming inducing particles on a side of the insulating layer group away from the base substrate; forming a doped amorphous silicon layer on a side of the inducing particles away from the base substrate, forming a first conductor part by the doped amorphous silicon layer formed in the first via hole, forming a raw material part by patterning the doped amorphous silicon layer; and forming a first channel part by causing the inducing particles to induce the raw material part, wherein the first channel part is connected to the first conductor part.

    THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS

    公开(公告)号:US20220406820A1

    公开(公告)日:2022-12-22

    申请号:US17779327

    申请日:2021-07-08

    Inventor: Yang LV

    Abstract: A thin film transistor includes a substrate and an active layer having a channel region. The active layer includes a first active pattern and at least one second active pattern. The first active pattern includes a bottom surface, a top surface and at least one side surface. The at least one side surface connects the bottom and top surfaces, and is in contact with the at least one second active pattern. A length direction of each side surface is approximately perpendicular to a length direction of the channel region. A material of at least the top surface of the first active pattern includes a first polysilicon material, and a material of the second active pattern includes a second polysilicon material; and in the length direction of the channel region, an average grain size of the first polysilicon material is greater than an average grain size of the second polysilicon material.

    THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE

    公开(公告)号:US20220115413A1

    公开(公告)日:2022-04-14

    申请号:US17263748

    申请日:2020-03-27

    Abstract: A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.

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