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公开(公告)号：US20250017069A1
公开(公告)日：2025-01-09
申请号：US18705621
申请日：2023-05-19
Inventor： Yipeng CHEN , Hui LU , Ling SHI
Abstract: A display substrate is provided, the display substrate has a display region and includes a base substrate, sub-pixels, data lines, and first signal lines; each of at least part of the sub-pixels includes a pixel driving circuit and a light-emitting device; the data lines are in a first metal layer, the first signal lines are in a second metal layer; in a first display region, a plurality of first signal lines extend in a first direction, the first display region includes first compensation patterns, the first electrode is on a side of the first signal lines and the first compensation patterns away from the base substrate, an orthographic projection of at least one first compensation pattern on the base substrate at least partially overlaps with an orthographic projection of the first electrode of a light-emitting device of at least one sub-pixel on the base substrate.
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公开(公告)号：US20240407196A1
公开(公告)日：2024-12-05
申请号：US18798917
申请日：2024-08-09
Inventor： Yipeng CHEN , Ling SHI , Wenqiang LI
IPC: H10K59/121 , H10K59/12 , H10K59/131
Abstract: An array substrate includes a pixel driving circuit, a base substrate, a first conductive layer, a first dielectric layer, a second conductive layer, and a data line. The pixel driving circuit includes a driving transistor, a first transistor, a capacitor, and a second transistor. The first conductive layer is laminated at a side of the base substrate and includes a first conductive portion. The first dielectric layer is laminated at a side of the first conductive layer away from the base substrate. The second conductive layer is laminated at a side of the first dielectric layer away from the base substrate, and includes a fourth gate line. The first conductive layer further includes a first gate line. An orthographic projection of the first gate line on the base substrate is located between orthographic projections of the fourth gate line and the first conductive portion on the base substrate.
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公开(公告)号：US20240381709A1
公开(公告)日：2024-11-14
申请号：US18033078
申请日：2022-05-31
Inventor： Yanhong DING , Hui LU , Bin LIU , Yipeng CHEN , Jiandong BAO , Tao GAO , Lang LIU
IPC: H10K59/131 , H10K59/12
Abstract: Disclosed are a display substrate, a preparation method therefor and a display apparatus. The display substrate includes a shielding conductive layer and a functional structure layer, wherein the shielding conductive layer at least includes a first connection line, and the functional structure layer at least includes a data signal line and a second connection line; in a plane parallel to the display substrate, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, the data signal line is connected to a plurality of pixel driving circuits of one unit column, the data signal line is configured to provide a data signal to the pixel driving circuit; the second connection line is connected with the first connection line, and the data signal line is connected with the second connection line.
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公开(公告)号：US20240297173A1
公开(公告)日：2024-09-05
申请号：US17795887
申请日：2021-09-18
Inventor： Hui LU , Yipeng CHEN , Shuai XIE , Fei FANG , Shuo LI , Xuewei TIAN , Ling SHI
IPC: H01L27/12 , G09G3/3233 , H10K59/131
CPC classification number: H01L27/1225 , G09G3/3233 , H01L27/124 , H01L27/127 , H10K59/131 , G09G2300/0426 , G09G2300/0465 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08 , G09G2320/0233 , G09G2320/0247 , G09G2330/021
Abstract: A display substrate, a manufacturing method therefor, and a display apparatus are provided. The display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on an substrate. The first semiconductor layer includes active layers of a plurality of poly silicon transistors, the first conductive layer includes gates of a plurality of poly silicon transistors, a first electrode plate of a storage capacitor and a first scan signal line. The second conductive layer includes a second electrode plate of the storage capacitor. The second semiconductor layer includes active layers of a plurality of oxide transistors. The third conductive layer includes gates of the plurality of oxide transistors.
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公开(公告)号：US20240265873A1
公开(公告)日：2024-08-08
申请号：US18020971
申请日：2022-01-29
Inventor： Yipeng CHEN , Hui LU , Ling SHI
IPC: G09G3/3266 , G11C19/28 , H01L27/12
CPC classification number: G09G3/3266 , G11C19/287 , H01L27/1225 , H01L27/1229 , H01L27/124 , H01L27/1259 , G09G2300/0426 , G09G2300/0819 , G09G2300/0861 , G09G2310/0286 , G09G2310/08 , G09G2320/045 , G09G2330/02
Abstract: A display substrate and a manufacturing method thereof, and a display device are provided. The display substrate includes a gate driving circuit including shift register units and clock signal lines including a first clock signal line, a second clock signal line providing a second clock signal, and a third clock signal line providing a third clock signal. An input circuit of a n-th stage shift register unit in the shift register units is connected with the first clock signal line, a first control circuit of the n-th stage shift register unit is connected with the first clock signal line, the second clock signal line, and the third clock signal line, a second control circuit of the n-th stage shift register unit is connected with the second clock signal line, and a phase of the second clock signal is opposite to a phase of the third clock signal.
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Patent Agency Ranking
公开(公告)号：US20230269985A1
公开(公告)日：2023-08-24
申请号：US17922508
申请日：2021-11-19
Inventor： Yipeng CHEN , Ling SHI , Ke LIU , Hui LU
IPC: H10K59/35 , H10K59/131
CPC classification number: H10K59/353 , H10K59/131
Abstract: The present disclosure relates to the field of display technology, and provides a display panel and a display device. The display panel includes a first display area and a second display area, and further includes a plurality of first pixel islands. The first pixel islands are in the first display area and include: at least one first light-emitting unit; at least one first pixel driving circuit, arranged in a one-to-one correspondence with the at least one first light-emitting unit, and configured to provide a driving current to a first light-emitting unit corresponding thereto; and a plurality of first signal line segments configured to provide signals to the at least one first pixel driving circuit.
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公开(公告)号：US20230020923A1
公开(公告)日：2023-01-19
申请号：US17948576
申请日：2022-09-20
Applicant: BOE Technology Group Co., Ltd.
Inventor： Yipeng CHEN , Lujiang HUANGFU , Libin LIU
IPC: H01L27/32 , G09G3/3233
Abstract: A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.
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公开(公告)号：US20220367596A1
公开(公告)日：2022-11-17
申请号：US17762692
申请日：2021-04-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Yipeng CHEN , Lujiang HUANGFU , Libin LIU
IPC: H01L27/32
Abstract: The present disclosure provides a display panel and a method of manufacturing the same and a display device. In a sub-pixel driving circuit of the display panel, a gate electrode of a driving transistor is coupled to a second electrode of a second transistor through a fourth conductive connection portion, and a second electrode plate of a storage capacitor is coupled to a second electrode of a first transistor through a third conductive connection portion, a gate electrode of the first transistor and a gate electrode of the second transistor are respectively coupled to a gate line pattern in the corresponding sub-pixel area; orthographic projection of the gate line pattern on the substrate does not overlap orthographic projection of the third conductive connecting portion on the substrate, and/or does not overlap orthographic projection of the fourth conductive connection portion on the substrate.
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公开(公告)号：US20210020108A1
公开(公告)日：2021-01-21
申请号：US17043071
申请日：2020-02-24
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yipeng CHEN , Libin LIU , Lujiang HUANGFU
IPC: G09G3/3258 , G09G3/3291 , G09G3/20
Abstract: The present disclosure provides a pixel circuit including: a driving transistor and a voltage control circuit; wherein in the voltage control circuit, at least one transistor directly coupled to a gate of the driving transistor is an oxide thin film transistor. The disclosure also provides a display substrate and a display apparatus.
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公开(公告)号：US20210020090A1
公开(公告)日：2021-01-21
申请号：US16651816
申请日：2019-03-25
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang SHANG , Libin LIU , Can ZHENG , Yipeng CHEN , Xinshe YIN , Shiming SHI
Abstract: Provided are a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an input circuit, configured to be coupled to an input signal end and a second clock signal end, respectively; a first transistor, where the first electrode of the first transistor is coupled to the output end of the input circuit, and the first transistor is a double-gate type transistor; the first gate of the first transistor is configured to be coupled to a first reference signal end, and the second gate of the first transistor is configured to be coupled to a first threshold control signal end; and an output circuit, configured to be coupled to a first clock signal end and a signal output end, respectively, where the control end of the output circuit is coupled to the second electrode of the first transistor.
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