Abstract:
A semiconductor memory cell is adapted for associative memory use by applying interrogation input information on the normal cell digit circuits that are also used for reading and writing operations. A pair of interrogation transistors compare digit circuit signals to the prevailing state of the cell and provide a corresponding indicator signal to a memory match signal bus. Several techniques are disclosed for realizing advantageous coupling between the interrogation transistors and the match bus and for implementing a match detector circuit for use with the bus. The several techniques, in conjunction with the use of insulated gate field effect transistors and the multipurpose digit circuits, are employed in different sets of circumstances to achieve different operating features.