公开(公告)号：US11782845B2

公开(公告)日：2023-10-10

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Joseph Michael Pusdesris ,  Abhishek Raja ,  Karthik Sundaram ,  Anoop Ramachandra Iyer ,  Michael Brian Schinzler ,  James David Dundas ,  Yasuo Ishii

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

公开(公告)号：US12159141B2

公开(公告)日：2024-12-03

申请号：US17949874

申请日：2022-09-21

Applicant: Arm Limited

Inventor： James David Dundas ,  Yasuo Ishii ,  Michael Brian Schinzler

IPC: G06F9/38

Abstract: A data processing apparatus includes control flow prediction circuitry that generates a control flow prediction in respect of a group of one or more instructions. Storage circuitry used by the control flow prediction circuitry stores data in association with groups of instructions used to generate the control flow prediction for each of the groups of instructions. Control flow prediction update circuitry inserts new data into the storage circuitry in association with a new group of one or more instructions in dependence on one or more conditions being met when a miss occurs for the group of one or more instructions in the storage circuitry.

公开(公告)号：US11861368B2

公开(公告)日：2024-01-02

申请号：US17752060

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Houdhaifa Bouzguarrou ,  Michael Brian Schinzler ,  Yasuo Ishii ,  Jatin Bhartia ,  Sumanth Chengad Raghu

IPC: G06F9/38 ,  G06F21/50 ,  G06F9/48

CPC classification number: G06F9/3848 ,  G06F9/3844 ,  G06F9/3806 ,  G06F9/48 ,  G06F21/50

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

公开(公告)号：US11507372B2

公开(公告)日：2022-11-22

申请号：US17064983

申请日：2020-10-07

Applicant: Arm Limited

Inventor： Michael Brian Schinzler ,  Yasuo Ishii ,  Muhammad Umar Farooq ,  Jason Lee Setter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle. The dispatch circuitry has resource checking circuitry arranged, by default, to perform a resource checking operation during the given dispatch cycle to generate, for the given candidate sequence of decoded instructions, resource conflict information used to determine whether a resource conflict would occur. Resource conflict information cache storage is provided to maintain, for one or more sequences of decoded instructions, associated resource conflict information. In the event that the given candidate sequence matches one of the sequences for which associated resource conflict information is cached, the dispatch circuitry employs the associated cached resource conflict information to determine whether a resource conflict would occur, instead of invoking the resource checking circuitry to perform the resource checking operation.

公开(公告)号：US12045620B2

公开(公告)日：2024-07-23

申请号：US17554573

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  William Elton Burky ,  Michael Brian Schinzler ,  Jason Lee Setter ,  David Gum Lim

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3867

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

公开(公告)号：US11237974B2

公开(公告)日：2022-02-01

申请号：US16552001

申请日：2019-08-27

Applicant: Arm Limited

Inventor： Michael Brian Schinzler ,  Michael Filippo

IPC: G06F12/0875 ,  G06F9/30 ,  G06F9/28

Abstract: A data processing apparatus is provided. The data processing apparatus includes fetch circuitry to fetch instructions from storage circuitry. Decode circuitry decodes each of the instructions into one or more operations and provides the one or more operations to one or more execution units. The decode circuitry is adapted to decode at least one of the instructions into a plurality of operations. Cache circuitry caches the one or more operations and at least one entry of the cache circuitry is a compressed entry that represents the plurality of operations.

公开(公告)号：US11003454B2

公开(公告)日：2021-05-11

申请号：US16514124

申请日：2019-07-17

Applicant: Arm Limited

Inventor： Michael Brian Schinzler ,  Michael Filippo ,  Yasuo Ishii

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatuses for data processing and methods of data processing are provided. A data processing apparatus performs data processing operations in response to a sequence of instructions including performing speculative execution of at least some of the sequence of instructions. In response to a branch instruction the data processing apparatus predicts whether or not the branch is taken or not taken further speculative instruction execution is based on that prediction. A path speculation cost is calculated in dependence on a number of recently flushed instructions and a rate at which speculatively executed instructions are issued may be modified based on the path speculation cost.

公开(公告)号：US12288073B2

公开(公告)日：2025-04-29

申请号：US18129979

申请日：2023-04-03

Applicant: Arm Limited

Inventor： Chang Joo Lee ,  Jason Lee Setter ,  Julia Kay Lanier ,  Michael Brian Schinzler ,  Yasuo Ishii

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus is provided for limiting the effective utilisation of an instruction fetch queue. The instruction fetch entries are used to control the prefetching of instructions from memory, such that those instructions are stored in an instruction cache prior to being required by execution circuitry while executing a program. By limiting the effective utilisation of the instruction fetch queue, fewer instructions will be prefetched and fewer instructions will be allocated to the instruction cache, thus causing fewer evictions from the instruction cache. In the event that the instruction fetch entries are for instructions that are unnecessary to the program, the pollution of the instruction cache with these unnecessary instructions can be mitigated.

公开(公告)号：US12204785B2

公开(公告)日：2025-01-21

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Steven Daniel Maclean ,  Nicholas Andrew Plante ,  Muhammad Umar Farooq ,  Michael Brian Schinzler ,  Nicholas Todd Humphries ,  Glen Andrew Harris

IPC: G06F3/06

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

公开(公告)号：US11915005B1

公开(公告)日：2024-02-27

申请号：US17960390

申请日：2022-10-05

Applicant: Arm Limited

Inventor： Chang Joo Lee ,  Michael Brian Schinzler ,  Yasuo Ishii ,  Sergio Schuler

IPC: G06F9/38

CPC classification number: G06F9/3844

Abstract: A data processing apparatus includes receive circuitry that receives an indication of a trigger block of instructions. Branch prediction circuitry provides, in response to the trigger block of instructions, branch predictions in respect of a branch within: a subsequent block of instructions subsequent to the trigger block of instructions in execution order, when in a 1-taken mode of operation and a later block of instructions subsequent to the subsequent block of instructions in execution order, when in a 2-taken mode of operation