公开(公告)号：US11132202B2

公开(公告)日：2021-09-28

申请号：US16580158

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Luca Nassi ,  Rémi Marius Teyssier ,  Cédric Denis Robert Airaud ,  Albin Pierrick Tonnerre ,  Francois Donati ,  Christophe Carbonne ,  Damian Maiorano

IPC: G06F9/38 ,  G06F12/0811 ,  G06F9/30

Abstract: An apparatus comprises execution circuitry to perform operations on source data values and to generate result data values; issue circuitry comprising one or more issue queues identifying pending operations awaiting performance by the execution circuitry, and selection circuitry to select pending operations to issue to the execution circuitry; data value cache storage comprising first and second cache regions; and cache control circuitry to control the storing to the first cache region of result data values generated by the execution circuitry and the eviction of stored result data values from the first cache region in response to newly generated result data values being stored in the first cache region; the cache control circuitry being configured to store to the second cache region result data values required as source data values for one or more oldest pending operations identified by the one or more issue queues and to inhibit eviction of a given result data value stored in the second cache region until initiation of execution of a pending operation which requires that given result data value as a source data value.