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公开(公告)号：US20200241589A1
公开(公告)日：2020-07-30
申请号：US16256675
申请日：2019-01-24
Applicant: Arm Limited
Inventor： Tushar P. Ringe , Ramamoorthy Guru Prasadh , Amaresh Pangal , Kishore Kumar Jagadeesha , Mark David Werkheiser
Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
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公开(公告)号：US10802534B2
公开(公告)日：2020-10-13
申请号：US16256675
申请日：2019-01-24
Applicant: Arm Limited
Inventor： Tushar P. Ringe , Ramamoorthy Guru Prasadh , Amaresh Pangal , Kishore Kumar Jagadeesha , Mark David Werkheiser
Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.
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公开(公告)号：US10585449B1
公开(公告)日：2020-03-10
申请号：US16248456
申请日：2019-01-15
Applicant: Arm Limited
Inventor： Tushar P. Ringe , Ramamoorthy Guru Prasadh , Amaresh Pangal , Kishore Kumar Jagadeesha , Mark David Werkheiser
Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.
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