公开(公告)号：US09406507B2

公开(公告)日：2016-08-02

申请号：US14661495

申请日：2015-03-18

Applicant: Applied Materials, Inc.

Inventor： Swaminathan T. Srinivasan ,  Fareen Adeni Khaja ,  Errol Antonio C. Sanchez ,  Patrick M. Martin

IPC: H01L29/267 ,  H01L21/02 ,  H01L21/311 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L21/02658 ,  H01J37/32082 ,  H01J37/32422 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31116 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/267 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

Abstract translation: 本公开的实施方案涉及减少异质外延生长膜中的位错密度和包括具有降低的位错密度的异质外延膜的器件。 根据本公开的实施例，高纵横比沟槽的侧壁可以倾斜或成角度，以允许在高纵横比沟槽中形成的结晶材料的缺陷在倾斜的侧壁中终止，包括沿着高方面的长度传播的缺陷 比例沟槽。 本公开的实施例可用于减少用于微电子应用的硅（Si）异质外延生长中的缺陷，例如在场效应晶体管中使用III-V族元素的高迁移率通道。

公开(公告)号：US20150162214A1

公开(公告)日：2015-06-11

申请号：US14560525

申请日：2014-12-04

Applicant: Applied Materials, Inc.

Inventor： David Thompson ,  Huixiong Dai ,  Patrick M. Martin ,  Timothy Michaelson ,  Kadthala R. Narendrnath ,  Robert Jan Visser ,  Jingjing Xu ,  Lin Zhang

IPC: H01L21/3213 ,  H01L21/3205

CPC classification number: H01L21/32051 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45551 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76849

Abstract: Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed.

Abstract translation: 提供了选择性沉积的方法。 某些方法描述了提供第一衬底表面; 提供第二衬底表面; 在所述第一和第二衬底表面上沉积第一层膜，其中所述沉积在所述第二衬底表面上具有孵育延迟，使得所述第一衬底表面上的所述第一层膜比沉积在所述第二衬底表面上的所述第一层膜厚 基材表面; 并且在所述第一和第二衬底表面上蚀刻所述第一层膜，其中所述第二衬底表面上的所述第一层膜至少被基本上去除，但所述第一衬底上的所述第一层膜仅被部分地去除。

公开(公告)号：US10026613B2

公开(公告)日：2018-07-17

申请号：US15668059

申请日：2017-08-03

Applicant: Applied Materials, Inc.

Inventor： Swaminathan T. Srinivasan ,  Fareen Adeni Khaja ,  Errol Antonio C. Sanchez ,  Patrick M. Martin

IPC: H01L21/02 ,  H01L21/311 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

公开(公告)号：US09799531B2

公开(公告)日：2017-10-24

申请号：US15195449

申请日：2016-06-28

Applicant: Applied Materials, Inc.

Inventor： Swaminathan T. Srinivasan ,  Fareen Adeni Khaja ,  Errol Antonio C. Sanchez ,  Patrick M. Martin

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267 ,  H01J37/32

CPC classification number: H01L21/02658 ,  H01J37/32082 ,  H01J37/32422 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02455 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/311 ,  H01L21/31116 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/267 ,  H01L29/78

Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.

公开(公告)号：US09716012B2

公开(公告)日：2017-07-25

申请号：US14560525

申请日：2014-12-04

Applicant: Applied Materials, Inc.

Inventor： David Thompson ,  Huixiong Dai ,  Patrick M. Martin ,  Timothy Michaelson ,  Kadthala R. Narendrnath ,  Robert Jan Visser ,  Jingjing Xu ,  Lin Zhang

IPC: H01L21/3205 ,  C23C16/04 ,  C23C16/18 ,  C23C16/455 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/32051 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45551 ,  C23C16/45553 ,  H01L21/28562 ,  H01L21/76849

Abstract: Provided are methods for selective deposition. Certain methods describe providing a first substrate surface; providing a second substrate surface; depositing a first layer of film over the first and second substrate surfaces, wherein the deposition has an incubation delay over the second substrate surface such that the first layer of film over the first substrate surface is thicker than the first layer of film deposited over the second substrate surface; and etching the first layer of film over the first and second substrate surfaces, wherein the first layer of film over the second substrate surface is at least substantially removed, but the first layer of film over the first substrate is only partially removed.

公开(公告)号：US20150275364A1

公开(公告)日：2015-10-01

申请号：US14666689

申请日：2015-03-24

Applicant: Applied Materials, Inc.

Inventor： David Thompson ,  Huixiong Dai ,  Patrick M. Martin ,  Timothy Michaelson ,  Kadthala R. Narendrnath ,  Robert Jan Visser ,  Jingjing Xu ,  Lin Zhang

IPC: C23C16/455 ,  C23C16/50 ,  C23C16/458

CPC classification number: C23C16/45544 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/4584 ,  C23C16/56 ,  H01L21/68764 ,  H01L21/68771

Abstract: Provided are apparatus and methods for the sequential deposition and annealing of a film within a single processing chamber. An energy source positioned within the processing chamber in an area isolated from process gases can be used to rapidly form and decompose a film on the substrate without damaging underlying layers due to exceeding the thermal budget of the device being formed.

Abstract translation: 提供了用于在单个处理室内顺序沉积和退火膜的装置和方法。 位于与处理气体隔离的区域内的处理室内的能量源可用于快速地形成和分解衬底上的膜，而不会由于超过正在形成的器件的热量预算而损坏下层。