公开(公告)号：US20250105870A1

公开(公告)日：2025-03-27

申请号：US18516182

申请日：2023-11-21

Applicant: Apple Inc.

Inventor： Yu Chang ,  Mitesh D. Katakwar ,  Huabo Chen ,  Huy M. Nguyen

IPC: H04B1/525 ,  H04L25/03

Abstract: Circuits for reflection cancellation in single-ended signaling are disclosed. A transmission circuit includes a control circuit configured to receive a plurality of input signals that include a plurality of symbols having at least one bit and a data driver circuit configured to generate a particular signal on a transmission medium using a particular symbol of the plurality of symbols. The transmission circuit further includes a reflection cancellation circuit configured to, after a generation of the particular signal, generate a reflection cancellation signal on the transmission medium using an inverted value of a different symbol of the plurality of symbols received prior to the particular symbol. A first composite of the particular signal and the cancellation signal is readable at a load as a value of the particular symbol, wherein the load is configured to receive a transmitted signal via the transmission medium.

公开(公告)号：US10727895B1

公开(公告)日：2020-07-28

申请号：US16585431

申请日：2019-09-27

Applicant: Apple Inc.

Inventor： Huy M. Nguyen ,  Cristian Gozzi ,  Huabo Chen ,  Xuchen Zhang ,  Yu Chang

IPC: H01L27/08 ,  H04B1/44 ,  H04L25/03 ,  H04B1/401

Abstract: A transceiver circuit having a T-coil circuit, inductive termination, and an equalization circuit is disclosed. The transceiver includes a transmitter having an output coupled to a first node, and a receiver having an input coupled to the first node. A T-coil circuit is coupled between the first node and an input/output (I/O) node. The T-coil circuit includes first and second inductors coupled in series between the first node and the I/O node, the inductors being coupled at a second node. A termination circuit is coupled between the first node and a reference node, the termination circuit including a third inductor. The transceiver circuit also includes an equalization circuit configured to convey an equalization signal to the second node.